Visible to Intel only — GUID: gsf1675714544406
Ixiasoft
Visible to Intel only — GUID: gsf1675714544406
Ixiasoft
8.5.1. HPS Reset Domains
The HPS contains multiple reset domains. A reset domain has one or more reset signals which are connected to one or more modules of the HPS. The SDM (POR, cold and warm) is the only external source of reset. The four HPS watchdogs are HW internal sources of reset. All the other resets are requested by software via control registers inside either the reset manager or the CPUs.
The following diagram shows the portions of the HPS that belongs to each reset domain. Boxes with square corners represent logical blocks, while boxes with rounded corners represent the reset domains listed in the table below. The warm, cold and POR domains are shown as proper supersets of each other.
The table below provides more detail for the individual reset domains. These domains are referenced in later sections providing more detail on the precise reset sequence.
Domain Name | Domain Logic | Source | Description |
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POR | Power-on-reset. All of HPS is reset by the power-on-reset domain. | SDM | SDM drives power-on-reset to the reset manager. POR domain is released when VCCL HPS POR and FPGA VCCL POR are both released. The main portion of the reset and clock manager are in the POR domain. Scratch registers, the secure manager, and system managers are in the POR domain. The TAP controller is in the POR domain. The PSI interface is in the POR domain. |
HPS cold reset | Cold Reset Domain. Almost all of the HPS is reset except:
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SDM requests reset manager to assert or de-assert cold reset to the system. |
HPS warm reset | Warm Reset Domain. Most of the HPS cold domain is reset except:
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Similar to cold reset with the exception that the debug domain is not impacted. Warm masks are available for MPFE, FPGA bridges. No warm masks for peripherals, watchdogs, and MPUs. Warm masks logic work for SDM warm reset, watchdog, and SW warm reset. |
SYSCFG cold reset | System Config Cold Reset Domain. The following are reset:
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Asserted during POR and HPS cold resets. |
SYSCFG warm reset | System Config Warm Reset Domain. The following are reset:
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Special domain for the system config NoC and system modules accessible by SDM. POR reset is treated as a "level" assertion of SYSCFG reset and the domain is not released until POR is released. After the release of POR reset but before cold/warm are released, SDM may only access the secure and shared modules in HPS. For SDM cold and warm reset assertions, the SYSCFG domain is asserted as an "edge" triggered reset. In other words, the SYSCFG domain is reset briefly and then immediately brought out of reset at the assertion of cold or warm resets. The rest of HPS treats cold/warm as "level" resets, so SDM may access the secure and shared modules shortly after the assertion of cold or warm reset but before they are de-asserted. |
Debug | HPS debug and trace logic outside of the DSU | Reset manager | May be asserted by cold reset, POR, software, or debugger. |
L3 | L3 interconnect reset for both main NOC and APS CCU/OCRAM/GIC. | Reset manager | Assert during POR, cold, and warm resets |
COREx cold | The logic in the individual cores, including the associated debug logic. | Reset manager | Asserts nCPUPORESET[3:0] inputs either during POR, cold, or to individual cores via software. |
COREx warm | The logic in the individual cores, not including the associated debug logic.
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Reset manager | Asserts nCORERESET[3:0] inputs either during POR, cold, warm, or to individual cores via software.
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L2 | DSU logic in GICCLK most of SCLK domains | Reset manager | Asserts l2reset_n during POR, cold, warm, or via software. |
FPER | Reset for fast peripheral blocks | Reset manager | Assertion during POR, cold, watchdog, and warm reset. De-assertion by SW. |
PER | Reset for peripheral blocks | Reset manager | Assertion during POR, cold, watchdog, and warm reset. De-assertion by SW. |
SPER | Reset for slow peripheral blocks | Reset manager | Assertion during POR, cold, watchdog, and warm reset. De-assertion by SW. |
Bridges | FPGA bridges and MPFE | Reset manager | Assertion during POR, cold, watchdog, warm reset, or via software. De-assertion by SW. |
TAP | JTAG TAP controller | Reset manager | Asserted with POR. |