Visible to Intel only — GUID: ate1708452640719
Ixiasoft
Visible to Intel only — GUID: ate1708452640719
Ixiasoft
8.7.5.3. HPS Pin-triggered Cold Reset
If the HPS_COLD_nRESET is asserted externally, then the SDM will put the HPS into reset, and wait for the external device to release the signal and allow it to be pulled high by the external pull-up resister. After this occurs, the SDM will change the HPS_COLD_nRESET signal to output and drive it low. At this point, referring to the Agilex™ 5 Configuration User Guide, the bitstream configuration file containing the FSBL must be resent to the SDM using the same interface that the MSEL[2:0] pins specified during POR. After the bitstream has been received, the SDM releases the HPS from reset, and the HPS_COLD_nRESET signal will be configured as an input and can be pulled high by the external pull-up resister. Note that the FPGA will not be disturbed during this process. The following figure shows the HPS pin-triggered cold reset behavior.