Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 11/27/2024
Public
Document Table of Contents

8.7.5.4. HPS Mailbox-triggered Cold Reset

If the cold reset is generated from internal sources (for example, a Mailbox command from the HPS software), the SDM switches this pin to output and drive a pulse to indicate reset. At this point, referring to the Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs , the bitstream configuration file containing the FSBL must be resent to the SDM using the same interface that the MSEL[2:0] pins specified during POR. Once the cold reset procedure is complete, this pin switches back to input and can be pulled high by the external pull-up resister. Note that the FPGA is not disturbed during this process. The following figure shows the HPS Mailbox-triggered cold reset behavior.

Figure 283.  HPS_COLD_nRESET Signal Behavior (HPS Mailbox-triggered Cold Reset)