Visible to Intel only — GUID: yca1676325959419
Ixiasoft
Visible to Intel only — GUID: yca1676325959419
Ixiasoft
11.5.1. FPGA-to-HPS Bridge
The F2H bridge provides access to the peripherals in HPS from the FPGA. This access is available to any manager implemented in the FPGA fabric. This bridge consists of a single physical ACE-Lite 256-bit non-configurable interface.
The figure below shows the F2H block diagram.
The following table shows the F2H bridge signals.
Name | Direction | Description |
---|---|---|
fpga2hps_clock | Input | Clock from a single source in the FPGA. |
fpga2hps_reset | Input | Async active high reset to the bridge. |
The following table lists the properties of the F2H bridge, including the interface exposed to the FPGA fabric.
Bridge Property | Value |
---|---|
Protocol | AMBA 4 AXI4, AMBA 4 ACE-Lite, AMBA 5 AXI5 |
Clock | fpga2hps_clock (from FPGA) |
Data width | 256-bit |
Address width | 40-bit |
ID width | 5-bit |
Fixed burst | No |
Min narrow burst size | 1 byte |
Max wrap burst length | 16 |
Read interleaving | Yes |
Ready latency requirement | Yes |
A*Region Width | 0 |
A*Len Width | 7 (256) |
A*QoS Width | 4 |
nPendingTrans (Issuance/Acceptance) | 16 |
nPendingOrderID | 16 |