Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

7.6.9. F2H User Clock Group

The F2H clock group contains clocks which are sourced from the FPGA and provided to the HPS.

The FPGA must be configured to drive clocks onto these FPGA-to-HPS clock interface signals via the GCLK, RCLK, and PCLK networks in the FPGA.

  • Global clock (GCLK): These clocks use global routing resources in the FPGA.
  • Regional clock (RCLK): These clocks route only to part of the chip, for example, the entire FPGA width and height of I/O tiles.
  • Periphery clock (PCLK): These clocks are for high-speed I/O interfaces.

There is one physical connection between the FPGA and HPS for each signal in the table below. Register settings within the HPS define how these clocks are used by the HPS.

Table 309.  F2H Clocks
Clock Name Clock Source HPS Destination Description
tpiu_trace_clkin Pin HPS TPIU Clocks all TPIU trace port transactions out of the HPS
emac[2:0]_phy_rxclk_i FPGA pin

EMAC

Peripherals

Clocks Ethernet MAC receive interface when MAC interface is routed through FPGA. GMII and RGMII RX CLK
emac[2:0]_phy_txclk_i FPGA pin

EMAC

Peripherals

Clocks Ethernet MAC transmit interface when MAC interface is routed through FPGA. GMII only TX CLK
emac_ptp_ref_clk

FPGA pin

-or-

FPGA PLL

EMAC0, EMAC1,

EMAC2

Timestamp

Clock mux

PTP reference clock for all EMACs. Must be used as timestamp clock if serial interface to FPGA is active.
f2h_free_clk FPGA PLL Clock manager Alternate clock source for PLLs. Must be clean high quality clock with less than or equal to +/- 2% jitter.