Visible to Intel only — GUID: hcv1679283215023
Ixiasoft
Visible to Intel only — GUID: hcv1679283215023
Ixiasoft
15.5.1. Debug APB
The debug APB is a network of debug and trace peripherals interconnected via the AMBA peripheral bus (APB) and allows a debugger to gain access to debug and trace system for auto-detection and configuration, as well as to offload trace data from the embedded trace FIFOs.
The diagram below shows the debug APB bus connectivity highlighted in orange color, and the debug access port (DAP) and APB-related IP blocks (Serial Wire JTAG-Debug Port (SWJ-DP), AMBA peripheral bus-access port (APB-AP), AXI-access port (AXI-AP), AMBA peripheral bus-interconnect (APB-IC’s), and ROM tables) highlighted in orange color.
The first section is made up of the SWJ-DP, 1x3 APB-IC, Main ROM table, APB-AP, and AXI-AP. This section is the CoreSight* debug access port (DAP).
The DAP connects to the second APB-IC which includes connections to the debug peripheral ROM table, CoreSight* debug and trace system, and to the FPGA 1x2 APB-IC.
The FPGA APB-IC includes a FPGA ROM table and a link to the FPGA fabric and can be used to access CoreSight* -compatible debug and trace system in the fabric.
An APB interconnect provides connections from a debugger, connected through the CoreSight* debug access port (DAP) or an on-chip debug agent connected via the PSS NoC, to the CoreSight* debug and trace system.
In addition, the CoreSight debug and trace system has an APB connection to the soft IP within the FPGA fabric. For example, a soft IP can take advantage of the HPS CoreSight infrastructure for a debug session.