Visible to Intel only — GUID: jkk1675816371747
Ixiasoft
Visible to Intel only — GUID: jkk1675816371747
Ixiasoft
5.4.6.1.10. Command Queue Settings
The eMMC command queue settings are used to configure the eMMC command queue timer. The SD/eMMC host controller read-only registers associated with these inputs are not modifiable by software, and these inputs are driven by a register in the system manager.
Signal Name | Register Bit Name | Default Value | Description |
---|---|---|---|
hwinit_itcfmul[3:0] | ITCMFMUL | 4’b0000 | ITCFMUL – Internal Timer Clock Frequency Multiplier (ITCFMUL) Defines the multiplier of internal clock frequency for the coalescing timer and for the SQS polling period. 0 – 0.001 MHz 1 – 0.01 MHz 2 – 0.1 MHz 3 – 1 MHz 4 – 10 MHz The ITCFMUL and ITCFVAL define the clock frequency. Default is 50 KHz |
hwinit_itcfval[9:0] | ITCMFVAL | 10’h32 | ITCFVAL – Internal Timer Clock Frequency Value (ITCFVAL) Value defines internal clock frequency for the coalescing timer and for the SQS polling period. The frequency is equal to ITCFMUL * ITCFVAL. |
hwinit_itcfsel[3:0] | ITCFSEL | 1’b0 | ITCFSEL – This is a system clock divider value. The internal timer clock frequency equals to clk (when hwinit_itcfsel=0) and clk/2(hwinit_itcfsel-1 ) where clk is the main SD/eMMC controller clock. |