Visible to Intel only — GUID: res1679439910393
Ixiasoft
Visible to Intel only — GUID: res1679439910393
Ixiasoft
5.8.6.5.9.2. Broadcast CCC Write Transfers
The broadcast CCC write transfers are initiated on the bus based on the COMMAND_PORT settings as shown in the following table.
Command Attribute | Bit-Field | Programmed Value | Description |
---|---|---|---|
Transfer command | CP | 1 | Indicates the controller to consider the CMD field. |
CMD[14] | 0 | Indicates the controller that the transfer is broadcast CCC transfer. | |
CMD[13:7] | 0x0 – 0x7F | Indicates the CCC command to be transferred. | |
DEV_INDX/ SLV_ADDR |
NA | This field is not used since the transfer isbBroadcast CCC. | |
MODE | 0 (SDR0) | Indicates the controller that the transfer should go in SDR mode.
Note: All CCC transfers are initiated with SDR0 speed.
|
|
CMD_ATTR | 0 or 1 |
|
|
RnW | 0 | Indicates the transfer is either write or read transfer.
|
|
Regular transfer (CMD_ATTR=0) |
DATA_LENGTH | 0 - 65535 | Indicates the transfer length of the transfer. |
Immediate transfer (CMD_ATTR=1) |
BYTE_CNT | 0 to 4 | Indicates the respective data bytes of immediate command are valid. |
Data in Tx-FIFO (regular transfer) or data bytes (immediate data transfer) are not required for some broadcast CCC’s which do not have payload data indicated through data length (regular transfer) or BYTE_CNT (immediate transfer). If the broadcast CCC does not consist of payload, you must indicate it with zero in either data length or BYTE_CNT fields based on the command issued.
The I3C controller halts in case of receiving NACK (it means no I3C device on the bus) for the address header of the broadcast CCC transfer. The controller updates the ERR_STS field with appropriate error information in the response status, halts the controller and gives back the control to the application to resume the operation of controller through writing ‘1’ to the RESUME bit of the HC_CONTROL register.