Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

4.1.5.4.2.1. Address Map When Using a Single SDRAM Channel

When the HPS is configured to use a single 16-bit SDRAM channel, then all traffic must be directed to the DMI0 port. This enables the MPFE to route the requests to the appropriate IOBank AXI4 port. The address map for this case is shown in the following figure.

Figure 24. Address Map When Using a Single SDRAM Channel

The left-hand column represents the HPS address map from the user’s perspective. The center column shows how the various segments of the address map are to be assigned to the various CCU target ports. The right-hand column shows how MPFE traffic being appears on the DMI0, DMI1, and DII1 target ports. This is the only supported CCU configuration for the single SDRAM channel configuration. In this case, there is a single memory interleave group (MIG0) that contains DMI0, and a single memory interleave group set (MIGS1) that contains MIG0. MIGS1 = [{DMI0}].