Visible to Intel only — GUID: kyd1679383149219
Ixiasoft
Visible to Intel only — GUID: kyd1679383149219
Ixiasoft
5.8.6.5.5. Aborting Transfers of I3C Master
The application of the master can request the controller to abort any ongoing I3C bus transfer by setting DEVICE_CTRL[ABORT] bit.
In response to an abort request, the controller issues the STOP condition after the on-going data byte is transferred or received. The controller then generates an interrupt, sets the INTR_STATUS[TRANSFER_ABORT_STS] bit and enters the halt state.
The controller then waits for the application to issue the resume command by setting the DEVICE_CTRL[RESUME] bit to exit the halt state. The application is expected to flush/drain all the queues and the FIFOs before programming the DEVICE_CTRL/HC_CONTROL[RESUME] bit to resume the controller.