Visible to Intel only — GUID: rnm1704263797726
Ixiasoft
1. Quick Start Guide
2. 10M/100M/1G Ethernet Design Example
3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example
5. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example
7. Interface Signals Description
8. Configuration Registers Description
9. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
Visible to Intel only — GUID: rnm1704263797726
Ixiasoft
1.4.1. Procedure
To change the target device in your hardware design example, follow these steps:
- Ensure hardware design example generation is complete.
- In the Quartus® Prime Pro Edition software, open the Quartus® Prime project <design_example_dir>/altera_eth_top.qpf.
- On the Processing menu, click Start Compilation.
- After a successful compilation, a.sof file is available in intel_eth_em10g32_0_EXAMPLE_DESIGN/<LL10G_*>/altera_eth_top.qpf directory. Follow these steps to program the hardware design example on the Agilex™ 5 device:
- On the Tools menu, click Programmer.
- In the Programmer, click Hardware Setup.
- Select a programming device.
- Select and add the Agilex 5 FPGA E-Series 065B Premium Development Kit (ES1) to which your Quartus® Prime Pro Edition session can connect.
- Ensure that Mode is set to JTAG.
- Select the device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
- In the row with your .sof, check the box for the .sof.
- Check the box in the Program/Configure column.
- Click Start.