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1. Quick Start Guide
2. 10M/100M/1G Ethernet Design Example
3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example
5. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example
7. Interface Signals Description
8. Configuration Registers Description
9. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
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7.4. PHY Interface Signals
Signal | Direction | Width | Description |
---|---|---|---|
rx_serial_data rx_serial_data_n |
In | [NUM_CHANNELS][1] |
RX serial input data |
tx_serial_data tx_serial_data_n |
Out | [NUM_CHANNELS][1] |
TX serial output data |
xcvr_mode | In | [NUM_CHANNELS][2] | Configures the transceiver operating mode. 2'b00: 1G 2'b01: 2.5G |
xcvr_mode_out | Out | [NUM_CHANNELS][2] | Outputs the current transceiver operating mode. 2'b00: 1G 2'b01: 2.5G |
serial_i_rx_serial_data serial_i_rx_serial_data |
In | [NUM_CHANNELS][1] | RX serial input data. |
serial_o_tx_serial_data serial_o_tx_serial_data |
Out | [NUM_CHANNELS][1] | TX serial output data. |