Visible to Intel only — GUID: xov1718260252070
Ixiasoft
1. Quick Start Guide
2. 10M/100M/1G Ethernet Design Example
3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example
5. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example
7. Interface Signals Description
8. Configuration Registers Description
9. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
Visible to Intel only — GUID: xov1718260252070
Ixiasoft
5.2. Hardware and Software Requirements
Altera uses the following hardware and software to test the design example in a Linux system:
- Quartus® Prime Pro Edition software
- QuestaSim* , VCS* MX, and Xcelium* simulators
- For hardware testing:
- Agilex™ 5 FPGA E-Series 065B Premium Development Kit (ES1) (A5ED065BB32AE6SR0)
- QSFP28 module on bank 1A