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1. Quick Start Guide
2. 10M/100M/1G Ethernet Design Example
3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example
5. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
6. Interface Signals Description
7. Configuration Registers Description
8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5
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1.2.2. Design Example Parameters
Parameter | Description |
---|---|
Select Design | Available example designs for the IP parameter settings. When you select an example design from the Preset library, this field shows the selected design. |
Example Design Files | The files to generate for the different development phase.
|
Generate File Format | The format of the RTL files for simulation—Verilog or VHDL. |
Select Board | Supported hardware for design implementation. When you select an Intel FPGA development board, the Target Device is the one that matches the device on the Development Kit. If this menu is not available, there is no supported board for the options that you select. No Development Kit : This option excludes the hardware aspects for the design example. |
Change Target Device | Select this parameter to display and select all devices for the Intel® FPGA IP development kit. |
Specify Number of Channels | The number of Ethernet channels. For Agilex™ 5 devices, the default number of channels is 2 and this parameter is not selectable. |