Visible to Intel only — GUID: nfa1448440083067
Ixiasoft
Visible to Intel only — GUID: nfa1448440083067
Ixiasoft
1.2.2. Design Example Parameters
Parameter | Description |
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Select Design | Available example designs for the IP parameter settings. When you select an example design from the Preset library, this field shows the selected design. |
Example Design Files | The files to generate for the different development phase.
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Generate File Format | The format of the RTL files for simulation—Verilog or VHDL. |
Generate Debug Signal Tap | This option provides a default signal tap analyzer with pre-identified debug signals for the design example altera_eth_top.stp file generated in the project folder. |
Select Board | Supported hardware for design implementation. When you select an Intel FPGA development board, the Target Device is the one that matches the device on the Development Kit. If this menu is not available, there is no supported board for the options that you select. Agilex 5 FPGA E-Series 065B Premium Development Kit (ES1) : This option allows you to test the design example on the selected Intel FPGA IP development kit. This option automatically selects the Target Device to match the device on the Intel® FPGA IP development kit. If your board revision has a different device grade, you can change the target device. None: This option excludes the hardware aspects for the design example. |
Select Device Initialization Clock | 25 MHz, 100 MHz, or 125 MHz external clock to the OSC_CLK_1 device pin for design example that uses transceivers. |
Change Target Device | Select this parameter to display and select all devices for the Intel® FPGA IP development kit. |
Specify Number of Channels | The number of Ethernet channels. For Agilex™ 5 devices, the default number of channels is 2 and this parameter is not selectable. |