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1. Quick Start Guide
2. 10M/100M/1G Ethernet Design Example
3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example
5. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example
7. Interface Signals Description
8. Configuration Registers Description
9. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
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6.3.1. Design Components
Component | Description |
---|---|
LL 10GbE MAC | The Low Latency Ethernet 10G MAC Intel® FPGA IP with the following configuration:
For the design example with the IEEE 1588v2 feature, the following additional parameters are configured:
|
PHY | The 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP with the following configuration:
|
Channel address decoder | Decodes the addresses of the components in each Ethernet channel, such as PHY and LL 10GbE MAC. |
Multi-channel address decoder | Decodes the addresses of the components used by all channels. |
Top address decoder | Decodes the addresses of the top-level components, such as the Traffic Controller. |
System PLL | GTS System PLL Clocks Intel® FPGA IP that generates reference clock and system PLL clocks for the Agilex™ 5 transceiver. |
Design Components for the IEEE 1588v2 Feature | |
Master ToD | The master ToD for all channels. |
ToD Synch | Synchronizes the master ToD to all local ToDs. |
Local ToD | The ToD for each channel. |
PTP Packet Classifier | Decodes the packet type of incoming PTP packets and returns the decoded information to the LL 10GbE MAC Intel® FPGA IP. |