3.2. IP Comparison Between Cyclone® V and Agilex™ 5 Devices
The list of IP cores supported in Quartus® Prime Standard Edition and Quartus® Prime Pro Edition differ due to the device families each Quartus® Prime version supports. Depending on the reuse capability of the IP cores, you can upgrade some designs immediately from Quartus® Prime Standard Edition to Quartus® Prime Pro Edition. However, in some designs, you must remove existing Quartus® Prime Standard Edition IP cores and replace them with IPs available only in the Quartus® Prime Pro Edition.
Note:
You cannot upgrade IP cores instantiated in the Quartus® Prime Pro Edition software version 23.2.1 to 23.4. Regenerate the instantiated IPs to proceed with your project. However, IP auto-upgrade will upgrade IPs from 23.4 to 24.1 and later releases.
The IP reuse action guideline in the following table is only applicable if you are migrating to Agilex™ 5 device or reusing IPs from Cyclone® V in Agilex™ 5 devices.
The following table compares available Cyclone® V IPs in the Quartus® Prime Standard Edition and the equivalent Agilex™ 5 IPs that the Quartus® Prime Pro Edition support:
| Area | IP Name in Cyclone® V | IP Name in Agilex™ 5 | Status in Quartus® Prime Pro Edition Version 24.1 | IP Reuse Action Guideline | Relevant Document |
|---|---|---|---|---|---|
| Basic Functions | |||||
| Arithmetic | ALTERA_CORDIC | CORDIC Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | CORDIC Intel® FPGA IP User Guide |
| Arithmetic | ALTFP_ABS | Floating Point Functions Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Floating Point Functions Intel® FPGA IP. | Floating-Point IP Cores User Guide |
| Arithmetic | ALTFP_ADD_SUB | Floating Point Functions Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Floating Point Functions Intel® FPGA IP. | Floating-Point IP Cores User Guide |
| Arithmetic | ALTFP_ATAN | Floating Point Functions Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Floating Point Functions Intel® FPGA IP. | Floating-Point IP Cores User Guide |
| Arithmetic | ALTFP_COMPARE | Floating Point Functions Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Floating Point Functions Intel® FPGA IP. | Floating-Point IP Cores User Guide |
| Arithmetic | ALTFP_CONVERT | Floating Point Functions Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Floating Point Functions Intel® FPGA IP. | Floating-Point IP Cores User Guide |
| Arithmetic | ALTFP_DIV | Floating Point Functions Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Floating Point Functions Intel® FPGA IP. | Floating-Point IP Cores User Guide |
| Arithmetic | ALTFP_EXP | Floating Point Functions Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Floating Point Functions Intel® FPGA IP. | Floating-Point IP Cores User Guide |
| Arithmetic | ALTFP_INV | Floating Point Functions Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Floating Point Functions Intel® FPGA IP. | Floating-Point IP Cores User Guide |
| Arithmetic | ALTFP_INV_SQRT | Floating Point Functions Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Floating Point Functions Intel® FPGA IP. | Floating-Point IP Cores User Guide |
| Arithmetic | ALTFP_LOG | Floating Point Functions Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Floating Point Functions Intel® FPGA IP. | Floating-Point IP Cores User Guide |
| Arithmetic | ALTFP_MULT | Floating Point Functions Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Floating Point Functions Intel® FPGA IP. | Floating-Point IP Cores User Guide |
| Arithmetic | ALTFP_SINCOS | Floating Point Functions Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Floating Point Functions Intel® FPGA IP. | Floating-Point IP Cores User Guide |
| Arithmetic | ALTMEMMULT | LPM_MULT Intel® FPGA IP | N/A | Remove the existing IP and replace with the LPM_MULT Intel® FPGA IP. | Intel® FPGA Integer Arithmetic IP Cores User Guide |
| Arithmetic | ALTMULT_COMPLEX | ALTMULT_COMPLEX Intel® FPGA IP | Enabled | Remove the existing IP and replace with the ALTMULT_COMPLEX Intel® FPGA IP. | Intel® FPGA Integer Arithmetic IP Cores User Guide |
| Arithmetic | ALTSQRT | ALTSQRT Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Intel® FPGA Integer Arithmetic IP Cores User Guide |
| Arithmetic | LPM_ADD_SUB | LPM_ADD_SUB | Not enabled yet | Upgrade IP core to the latest version. | Intel® FPGA Integer Arithmetic IP Cores User Guide |
| Arithmetic | LPM_COMPARE | LPM_COMPARE | Not enabled yet | Upgrade IP core to the latest version. | Intel® FPGA Integer Arithmetic IP Cores User Guide |
| Arithmetic | LPM_COUNTER | LPM_COUNTER Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Intel® FPGA Integer Arithmetic IP Cores User Guide |
| Arithmetic | LPM_DIVIDE | LPM_DIVIDE Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Intel® FPGA Integer Arithmetic IP Cores User Guide |
| Arithmetic | LPM_MULT | LPM_MULT Intel® FPGA IP | Enabled | Remove the existing IP and replace with the LPM_MULT Intel® FPGA IP. | Intel® FPGA Integer Arithmetic IP Cores User Guide |
| Arithmetic | PARALLEL_ADD | PARALLEL_ADD Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Intel® FPGA Integer Arithmetic IP Cores User Guide |
| Arithmetic | FP_ACC_CUSTOM Intel® FPGA IP | Floating Point Custom Accumulator Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Floating-Point IP Cores User Guide |
| Arithmetic | FP_FUNCTIONS Intel® FPGA IP | Floating Point Functions Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Floating-Point IP Cores User Guide |
| Arithmetic | Multiply Adder Intel® FPGA IP | Multiply Adder Intel® FPGA IP | Enabled | Remove the existing IP and regenerate the Multiply Adder Intel® FPGA IP. | Intel® FPGA Integer Arithmetic IP Cores User Guide |
| Arithmetic | ALTFP_SQRT | Floating Point Functions Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Floating Point Functions Intel® FPGA IP. | Floating-Point IP Cores User Guide |
| Bridges and Adapters/Clock | Clock Bridge | Clock Bridge Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Bridges and Adapters/Interrupt | IRQ Bridge | IRQ Bridge Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Bridges and Adapters/Memory Mapped | Address Span Extender | Address Span Extender Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Bridges and Adapters/Memory Mapped | Avalon-MM Clock Crossing Bridge | Avalon Memory Mapped Clock Crossing Bridge Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Bridges and Adapters/Memory Mapped | Avalon-MM Pipeline Bridge | Avalon Memory Mapped Pipeline Bridge Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Bridges and Adapters/Memory Mapped | Avalon-MM Unaligned Burst Expansion Bridge | Avalon Memory Mapped Unaligned Burst Expansion Bridge Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Bridges and Adapters/Memory Mapped | AXI Bridge | AXI Bridge Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Bridges and Adapters/Memory Mapped | AXI Timeout Bridge | AXI Timeout Bridge Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Bridges and Adapters/Memory Mapped | JTAG to Avalon Master Bridge | JTAG to Avalon Master Bridge Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Embedded Peripherals IP User Guide |
| Bridges and Adapters/Reset | Reset Bridge | Reset Bridge Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Bridges and Adapters/Streaming | Avalon Packets to Transaction Converter | Avalon Packets to Transaction Converter Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Bridges and Adapters/Streaming | Avalon-ST Adapter | Avalon Streaming Adapter Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Bridges and Adapters/Streaming | Avalon-ST Bytes to Packets Converter | Avalon-ST Bytes to Packets Converter Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Embedded Peripherals IP User Guide |
| Bridges and Adapters/Streaming | Avalon-ST Channel Adapter | Avalon Streaming Channel Adapter Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Bridges and Adapters/Streaming | Avalon-ST Data Format Adapter | Avalon Streaming Data Format Adapter Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Bridges and Adapters/Streaming | Avalon-ST Delay | Avalon Streaming Delay Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Bridges and Adapters/Streaming | Avalon-ST Demultiplexer | Avalon Streaming Demultiplexer Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Bridges and Adapters/Streaming | Avalon-ST Error Adapter | Avalon Streaming Error Adapter Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Bridges and Adapters/Streaming | Avalon-ST Multiplexer | Avalon Streaming Multiplexer Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Bridges and Adapters/Streaming | Avalon-ST Packets to Bytes Converter | Avalon-ST Packets to Bytes Converter Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Bridges and Adapters/Streaming | Avalon-ST Pipeline Stage | Avalon Streaming Pipeline Stage Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Bridges and Adapters/Streaming | Avalon-ST Splitter | Avalon Streaming Splitter Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Bridges and Adapters/Streaming | Avalon-ST Timing Adapter | Avalon Streaming Timing Adapter Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Clocks; PLLs and Resets | ALTCLKCTRL Intel® FPGA IP | Clock Control Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Clock Control Intel® FPGA IP. | Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs |
| Clocks; PLLs and Resets | Clock Source | N/A | N/A | Upgrade IP core to latest version or replace with Clock Bridge Intel® FPGA IP. | |
| Clocks; PLLs and Resets | Merlin Reset Controller | Reset Controller Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Clocks; PLLs and Resets | Reset Sequencer | Reset Sequencer Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Clocks; PLLs and Resets/PLL | PLL Intel® FPGA IP | IOPLL Intel® FPGA IP | Enabled | Remove the existing IP and replace with the IOPLL Intel® FPGA IP. | Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs |
| Clocks; PLLs and Resets/PLL | PLL Reconfig Intel® FPGA IP | Not supported | Not enabled yet | Remove the existing IP. | |
| Configuration and Programming | Advanced SEU Detection Intel® FPGA IP | Advanced SEU Detection Intel® FPGA IP | Enabled | Replace the ASD IP (altera_adv_seu_detection) to ASD IP (stratix10_asd). | Advanced SEU Detection Intel® FPGA IP User Guide |
| Configuration and Programming | Reset Release Intel® FPGA IP | Reset Release Intel® FPGA IP | Enabled | Replace the Reset Release Intel® FPGA IP (s10_user_rst_clkgate) with the Reset Release Intel FPGA IP (intel_user_rst_clkgate). | Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs |
| Configuration and Programming | ASMI Parallel II Intel® FPGA IP | Generic Serial Flash Interface Intel® FPGA IP | N/A | Remove the existing IP and replace with the Generic Serial Flash Interface Intel® FPGA IP. | Generic Serial Flash Interface Intel® FPGA IP User Guide |
| Configuration and Programming | ASMI Parallel Intel® FPGA IP | Generic Serial Flash Interface Intel® FPGA IP | N/A | Remove the existing IP and replace with the Generic Serial Flash Interface Intel® FPGA IP. | Generic Serial Flash Interface Intel® FPGA IP User Guide |
| Configuration and Programming | Error Message Register Unloader Intel® FPGA IP | Not supported | N/A | Remove the existing IP. | |
| Configuration and Programming | Fault Injection Intel® FPGA IP | Not supported | N/A | Remove the existing IP. | |
| Configuration and Programming | Generic Serial Flash Interface Intel® FPGA IP | Generic Serial Flash Interface Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Generic Serial Flash Interface Intel® FPGA IP User Guide |
| Configuration and Programming | Internal Oscillator | Configuration Clock Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Configuration Clock Intel® FPGA IP. | Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs |
| Configuration and Programming | Legacy EPCS/EPCQx1 Flash Controller Intel® FPGA IP | Generic Serial Flash Interface Intel® FPGA IP | N/A | Remove the existing IP and replace with the Generic Serial Flash Interface Intel® FPGA IP. | Generic Serial Flash Interface Intel® FPGA IP User Guide |
| Configuration and Programming | Parallel Flash Loader II Intel® FPGA IP | Parallel Flash Loader II Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Parallel Flash Loader Intel® FPGA IP User Guide |
| Configuration and Programming | Parallel Flash Loader Intel® FPGA IP | Not supported | N/A | Remove the existing IP. | |
| Configuration and Programming | Partial Reconfiguration Intel® FPGA IP | Partial Reconfiguration Controller Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Partial Reconfiguration Controller Intel® FPGA IP. | Quartus® Prime Pro Edition User Guide: Partial Reconfiguration |
| Configuration and Programming | Remote Update Intel® FPGA IP | Not supported | N/A | Remove the existing IP. | |
| Configuration and Programming | Serial Flash Controller II Intel® FPGA IP | Generic Serial Flash Interface Intel® FPGA IP | N/A | Remove the existing IP and replace with the Generic Serial Flash Interface Intel® FPGA IP. | Generic Serial Flash Interface Intel® FPGA IP User Guide |
| Configuration and Programming | Serial Flash Controller Intel® FPGA IP | Generic Serial Flash Interface Intel® FPGA IP | N/A | Remove the existing IP and replace with the Generic Serial Flash Interface Intel® FPGA IP. | Generic Serial Flash Interface Intel® FPGA IP User Guide |
| Configuration and Programming | Serial Flash Loader Intel® FPGA IP | Not supported | N/A | Remove the existing IP. | |
| Configuration and Programming | Unique Chip ID Intel® FPGA IP | Not supported | N/A | Remove the existing IP. | |
| I/O | ALTDDIO_BIDIR | GPIO Intel® FPGA IP | Enabled | Remove the existing IP and replace with the GPIO Intel® FPGA IP. | General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs |
| I/O | ALTDDIO_IN | GPIO Intel® FPGA IP | Enabled | Remove the existing IP and replace with the GPIO Intel® FPGA IP. | General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs |
| I/O | ALTDDIO_OUT | GPIO Intel® FPGA IP | Enabled | Remove the existing IP and replace with the GPIO Intel® FPGA IP. | General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs |
| I/O | ALTDLL | Not supported | N/A | Remove the existing IP. | |
| I/O | ALTIOBUF | GPIO Intel® FPGA IP | Enabled | Remove the existing IP and replace with the GPIO Intel® FPGA IP. | General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs |
| I/O | ALTLVDS_RX | LVDS SERDES Intel® FPGA IP | Enabled | Remove the existing IP and replace with the LVDS SERDES Intel® FPGA IP. | LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs |
| I/O | ALTLVDS_TX | LVDS SERDES Intel® FPGA IP | Enabled | Remove the existing IP and replace with the LVDS SERDES Intel® FPGA IP. | LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs |
| I/O | PHY Lite for Parallel Interfaces Intel® FPGA IP | PHY Lite for Parallel Interfaces Intel® FPGA IP | Enabled | Remove existing IP and regenerate PHY Lite for Parallel Interfaces Intel® FPGA IP. | PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide |
| I/O | ALTOCT | Not supported | N/A | Remove the existing IP. The function is part of PHY Lite for Parallel Interfaces Intel® FPGA IP. | |
| Miscellaneous | ALTECC | ALTECC Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Intel® FPGA Integer Arithmetic IP Cores User Guide |
| Miscellaneous | LPM_CLSHIFT | LPM_CLSHIFT Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | |
| Miscellaneous | LPM_CONSTANT | LPM_CONSTANT | Not enabled yet | Upgrade IP core to the latest version. | |
| Miscellaneous | LPM_DECODE | LPM_DECODE Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | |
| Miscellaneous | LPM_MUX | LPM_MUX | Not enabled yet | Upgrade IP core to the latest version. | |
| Miscellaneous | LPM_SHIFTREG | LPM_SHIFTREG Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | |
| DMA | DMA Controller Intel® FPGA IP | Not supported | N/A | Remove the existing IP and replace with the Scalable Scatter-Gather DMA Intel® FPGA IP. | Embedded Peripherals IP User Guide |
| DMA | Modular Scatter-Gather DMA Intel® FPGA IP | Modular Scatter-Gather DMA Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Embedded Peripherals IP User Guide |
| DMA | Scatter-Gather DMA Controller Intel® FPGA IP | Not supported | N/A | Remove the existing IP. | |
| DMA/mSGDMA Sub-core | Modular SGDMA Dispatcher Intel® FPGA IP | Modular SGDMA Dispatcher Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Embedded Peripherals IP User Guide |
| DMA/mSGDMA Sub-core | Modular SGDMA Prefetcher Intel® FPGA IP | Modular SGDMA Prefetcher Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Embedded Peripherals IP User Guide |
| DMA/mSGDMA Sub-core | Read Master Intel® FPGA IP | Read Master Intel® FPGA IP | Enabled | Upgrade IP core to the latest version.
Note: This IP supports AVMM master and slave mode, and not AXI.
|
|
| DMA/mSGDMA Sub-core | Write Master Intel® FPGA IP | Write Master Intel® FPGA IP | Enabled | Upgrade IP core to the latest version.
Note: This IP supports AVMM master and slave mode, and not AXI.
|
|
| On Chip Memory | Avalon FIFO Memory Intel® FPGA IP | Avalon FIFO Memory Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Embedded Peripherals IP User Guide |
| On Chip Memory | Avalon-ST Dual Clock FIFO | Avalon Streaming Dual Clock FIFO Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| On Chip Memory | Avalon-ST Multi-Channel Shared Memory FIFO | Avalon-ST Multi-Channel Shared Memory FIFO | Enabled | Upgrade IP core to the latest version. | Embedded Peripherals IP User Guide |
| On Chip Memory | Avalon-ST Round Robin Scheduler | Avalon-ST Round Robin Scheduler Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| On Chip Memory | Avalon-ST Single Clock FIFO | Avalon Streaming Single Clock FIFO Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| On Chip Memory | FIFO IP | FIFO Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | FIFO Intel® FPGA IP User Guide |
| On Chip Memory | RAM Initializer | Not supported | N/A | Remove the existing IP. | |
| On Chip Memory | RAM: 1-PORT | RAM: 1-PORT Intel® FPGA IP | Enabled | Remove the existing IP and replace with the RAM: 1-PORT Intel® FPGA IP. | Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs |
| On Chip Memory | RAM: 2-PORT | RAM: 2-PORT Intel® FPGA IP | Enabled | Remove the existing IP and replace with the RAM: 2-PORT Intel® FPGA IP. | Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs |
| On Chip Memory | ROM: 1-PORT | ROM: 1-PORT Intel® FPGA IP | Enabled | Remove the existing IP and replace with the ROM: 1-PORT Intel® FPGA IP. | Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs |
| On Chip Memory | ROM: 2-PORT | ROM: 2-PORT Intel® FPGA IP | Enabled | Remove the existing IP and replace with the ROM: 2-PORT Intel® FPGA IP. | Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs |
| On Chip Memory | Shift register (RAM-based) | Shift Register (RAM-based) Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Shift Register (RAM-based) Intel® FPGA IP. | Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs |
| On Chip Memory | On-Chip Memory (RAM or ROM) Intel® FPGA IP | On-Chip Memory II (RAM or ROM) Intel® FPGA IP | Enabled | Remove the existing IP and replace with the On-Chip Memory II (RAM or ROM) Intel® FPGA IP. | Embedded Peripherals IP User Guide |
| Simulation; Debug and Verification/Debug and Performance | Altera SignalTap II Logic Analyzer | Signal Tap Logic Analyzer Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Debug Tools |
| Simulation; Debug and Verification/Debug and Performance | Altera Soft Core JTAG IO | Soft Core JTAG I/O Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | |
| Simulation; Debug and Verification/Debug and Performance | Altera Virtual JTAG | Virtual JTAG Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Virtual JTAG Intel® FPGA IP Core User Guide |
| Simulation; Debug and Verification/Debug and Performance | Intel® FPGA In-System Sources & Probes | In-System Sources & Probes Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Debug Tools |
| Simulation; Debug and Verification/Debug and Performance | Performance Counter Unit Intel® FPGA IP | Performance Counter Unit Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Embedded Peripherals IP User Guide |
| Simulation; Debug and Verification/Debug and Performance | SLD Hub Controller | Not supported | N/A | Remove the existing IP. | |
| Simulation; Debug and Verification/Debug and Performance | SLD Hub Controller System | Not supported | N/A | Remove the existing IP. | |
| Simulation; Debug and Verification/Debug and Performance | System ID Peripheral Intel® FPGA IP | System ID Peripheral Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Embedded Peripherals IP User Guide |
| Simulation; Debug and Verification/Debug and Performance | Trace System | Trace System Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Video and Image Processing Suite User Guide |
| Simulation; Debug and Verification/Debug and Performance | USB Debug Link | USB Debug Link Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | |
| Simulation; Debug and Verification/Debug and Performance | USB Debug Master | USB Debug Master Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | |
| Simulation; Debug and Verification/Simulation | Altera Avalon MM Monitor | Altera Avalon-MM Monitor Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Avalon Verification IP Suite: User Guide |
| Simulation; Debug and Verification/Simulation | Avalon Interrupt Sink Intel® FPGA IP | Avalon Interrupt Sink Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Avalon Verification IP Suite: User Guide |
| Simulation; Debug and Verification/Simulation | Avalon Interrupt Source Intel® FPGA IP | Avalon Interrupt Source Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Avalon Verification IP Suite: User Guide |
| Simulation; Debug and Verification/Simulation | Avalon-MM Master BFM Intel® FPGA IP | Avalon-MM Master BFM Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Avalon Verification IP Suite: User Guide |
| Simulation; Debug and Verification/Simulation | Avalon-MM Slave BFM Intel® FPGA IP | Avalon-MM Slave BFM Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Avalon Verification IP Suite: User Guide |
| Simulation; Debug and Verification/Simulation | Avalon-ST Monitor Intel® FPGA IP | Avalon-ST Monitor Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Avalon Verification IP Suite: User Guide |
| Simulation; Debug and Verification/Simulation | Avalon-ST Sink BFM Intel® FPGA IP | Avalon-ST Sink BFM Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Avalon Verification IP Suite: User Guide |
| Simulation; Debug and Verification/Simulation | Avalon-ST Source BFM Intel FPGA IP | Avalon-ST Source BFM Intel FPGA IP | Enabled | Upgrade IP core to the latest version. | Avalon Verification IP Suite: User Guide |
| Simulation; Debug and Verification/Simulation | Clock Source BFM Intel FPGA IP | Clock Source BFM Intel FPGA IP | Enabled | Upgrade IP core to the latest version. | Avalon Verification IP Suite: User Guide |
| Simulation; Debug and Verification/Simulation | Conduit BFM Intel FPGA IP | Conduit BFM Intel FPGA IP | Enabled | Upgrade IP core to the latest version. | Avalon Verification IP Suite: User Guide |
| Simulation; Debug and Verification/Simulation | External Memory BFM Intel FPGA IP | External Memory BFM Intel FPGA IP | Enabled | Upgrade IP core to the latest version. | Avalon Verification IP Suite: User Guide |
| Simulation; Debug and Verification/Simulation | Mentor Graphics AXI3 Inline Monitor BFM ( Intel® FPGA Edition) | Mentor Graphics AXI3 Inline Monitor BFM ( Intel® FPGA Edition) | Enabled | Upgrade IP core to the latest version. | Siemens EDA* AXI Verification IP Suite |
| Simulation; Debug and Verification/Simulation | Mentor Graphics AXI3 Master BFM ( Intel® FPGA Edition) | Mentor Graphics AXI3 Master BFM ( Intel® FPGA Edition) | Enabled | Upgrade IP core to the latest version. | Siemens EDA* AXI Verification IP Suite |
| Simulation; Debug and Verification/Simulation | Mentor Graphics AXI3 Slave BFM ( Intel® FPGA Edition) | Mentor Graphics AXI3 Slave BFM ( Intel® FPGA Edition) | Enabled | Upgrade IP core to the latest version. | Siemens EDA* AXI Verification IP Suite |
| Simulation; Debug and Verification/Simulation | Mentor Graphics AXI4 Inline Monitor BFM ( Intel® FPGA Edition) | Mentor Graphics AXI4 Inline Monitor BFM ( Intel® FPGA Edition) | Enabled | Upgrade IP core to the latest version. | Siemens EDA* AXI Verification IP Suite |
| Simulation; Debug and Verification/Simulation | Mentor Graphics AXI4 Master BFM ( Intel® FPGA Edition) | Mentor Graphics AXI4 Master BFM ( Intel® FPGA Edition) | Enabled | Upgrade IP core to the latest version. | Siemens EDA* AXI Verification IP Suite |
| Simulation; Debug and Verification/Simulation | Mentor Graphics AXI4 Slave BFM ( Intel® FPGA Edition) | Mentor Graphics AXI4 Slave BFM ( Intel® FPGA Edition) | Enabled | Upgrade IP core to the latest version. | Siemens EDA* AXI Verification IP Suite |
| Simulation; Debug and Verification/Simulation | Mentor Graphics AXI4-lite Inline Monitor BFM ( Intel® FPGA Edition) | Mentor Graphics AXI4-lite Inline Monitor BFM ( Intel® FPGA Edition) | Enabled | Upgrade IP core to the latest version. | Siemens EDA* AXI Verification IP Suite |
| Simulation; Debug and Verification/Simulation | Mentor Graphics AXI4-lite Master BFM ( Intel® FPGA Edition) | Mentor Graphics AXI4-lite Master BFM ( Intel® FPGA Edition) | Enabled | Upgrade IP core to the latest version. | Siemens EDA* AXI Verification IP Suite |
| Simulation; Debug and Verification/Simulation | Mentor Graphics AXI4-lite Slave BFM ( Intel® FPGA Edition) | Mentor Graphics AXI4-lite Slave BFM ( Intel® FPGA Edition) | Enabled | Upgrade IP core to the latest version. | Siemens EDA* AXI Verification IP Suite |
| Simulation; Debug and Verification/Simulation | Mentor Graphics AXI4STREAM Inline Monitor BFM ( Intel® FPGA Edition) | Mentor Graphics AXI4STREAM Inline Monitor BFM ( Intel® FPGA Edition) | Enabled | Upgrade IP core to the latest version. | Siemens EDA* AXI Verification IP Suite |
| Simulation; Debug and Verification/Simulation | Mentor Graphics AXI4STREAM Master BFM ( Intel® FPGA Edition) | Mentor Graphics AXI4STREAM Master BFM ( Intel® FPGA Edition) | Enabled | Upgrade IP core to the latest version. | Siemens EDA* AXI Verification IP Suite |
| Simulation; Debug and Verification/Simulation | Mentor Graphics AXI4STREAM Slave BFM ( Intel® FPGA Edition) | Mentor Graphics AXI4STREAM Slave BFM ( Intel® FPGA Edition) | Enabled | Upgrade IP core to the latest version. | Siemens EDA* AXI Verification IP Suite |
| Simulation; Debug and Verification/Simulation | Nios II Custom Instruction Master BFM Intel® FPGA IP | Not supported | N/A | Remove the existing IP. | Avalon Verification IP Suite: User Guide |
| Simulation; Debug and Verification/Simulation | Nios II Custom Instruction Slave BFM Intel® FPGA IP | Not supported | N/A | Remove the existing IP. | Avalon Verification IP Suite: User Guide |
| Simulation; Debug and Verification/Simulation | Reset Source BFM Intel® FPGA IP | Reset Source BFM Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Avalon Verification IP Suite: User Guide |
| Simulation; Debug and Verification/Simulation | Tri-State Conduit BFM Intel® FPGA IP | Tri-State Conduit BFM Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Avalon Verification IP Suite: User Guide |
| Simulation; Debug and Verification/Verification | Altera Avalon Data Pattern Checker | Avalon Data Pattern Checker Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro EditionUser Guide: Platform Designer |
| Simulation; Debug and Verification/Verification | Altera Avalon Data Pattern Generator | Not supported | N/A | Remove the existing IP. | |
| Simulation; Debug and Verification/Verification | Avalon-MM Traffic Generator and BIST Engine | Not supported | N/A | Remove the existing IP. | |
| Simulation; Debug and Verification/Verification | Avalon-ST Test Pattern Checker | Not supported | N/A | Remove the existing IP. | |
| Simulation; Debug and Verification/Verification | Avalon-ST Test Pattern Generator | Not supported | N/A | Remove the existing IP. | |
| DSP | |||||
| Error Detection and Correction | BCH | Not supported | N/A | Remove the existing IP. | |
| Error Detection and Correction | High-Speed Reed-Solomon | Not supported | N/A | Remove the existing IP. | |
| Error Detection and Correction | Reed Solomon II | Not supported | N/A | Remove the existing IP. | |
| Error Detection and Correction | Turbo | Turbo Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Turbo Intel® FPGA IP User Guide |
| Error Detection and Correction | Viterbi | Not supported | N/A | Remove the existing IP. | |
| Filters | CIC | CIC Intel FPGA IP | Enabled | Upgrade IP core to the latest version. | DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook |
| Filters | FIR II | FIR II Intel FPGA IP | Enabled | Upgrade IP core to the latest version. | DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook |
| Floating Point | Floating Point Hardware 2 Combinatorial | Not supported | N/A | Remove the existing IP. | |
| Floating Point | Floating Point Hardware 2 Multi-cycle | Not supported | N/A | Remove the existing IP. | |
| Signal Generation | NCO | NCO Intel FPGA IP | Enabled | Remove the existing IP and replace with NCO Intel FPGA IP. | DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook |
| Transforms | FFT | FFT Intel FPGA IP | Enabled | Upgrade IP core to the latest version. | DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook |
| Video and Image Processing | 2D-FIR II (4K ready) Intel® FPGA IP | FIR Filter Intel® FPGA IP | Enabled | Remove the existing IP and replace with the FIR Filter Intel® FPGA IP. | Video and Vision Processing Suite Intel® FPGA IP User Guide |
| Video and Image Processing | Avalon-ST Video Monitor Intel® FPGA IP | Not supported | N/A | Remove the IP. | |
| Video and Image Processing | Avalon-ST Video Stream Cleaner Intel® FPGA IP | Stream Cleaner Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Stream Cleaner Intel® FPGA IP. | Video and Vision Processing Suite Intel® FPGA IP User Guide |
| Video and Image Processing | Chroma Resampler II (4K Ready) Intel® FPGA IP | Chroma Resampler Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Chroma Resampler Intel® FPGA IP. | Video and Vision Processing Suite Intel® FPGA IP User Guide |
| Video and Image Processing | Clipper II (4K Ready) Intel® FPGA IP | Clipper Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Clipper Intel® FPGA IP. | Video and Vision Processing Suite Intel® FPGA IP User Guide |
| Video and Image Processing | Clocked Video Input II (4K Ready) Intel® FPGA IP | Clocked Video Input Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Clocked Video Input Intel® FPGA IP. | Video and Vision Processing Suite Intel® FPGA IP User Guide |
| Video and Image Processing | Clocked Video Output II (4K Ready) Intel® FPGA IP | Clocked Video Output Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Clocked Video Output Intel® FPGA IP. | Video and Vision Processing Suite Intel® FPGA IP User Guide |
| Video and Image Processing | Color Plane Sequencer II (4K Ready) Intel® FPGA IP | Color Plane Manager Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Color Plane Manager Intel® FPGA IP. | Video and Vision Processing Suite Intel® FPGA IP User Guide |
| Video and Image Processing | Color Space Converter II (4K Ready) Intel® FPGA IP | Color Space Converter Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Color Space Converter Intel® FPGA IP. | Video and Vision Processing Suite Intel® FPGA IP User Guide |
| Video and Image Processing | Configurable Guard Bands (4K Ready) Intel® FPGA IP | Guard Bands Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Guard Bands Intel® FPGA IP. | Video and Vision Processing Suite Intel® FPGA IP User Guide |
| Video and Image Processing | Deinterlacer II (4K HDR passthrough) Intel® FPGA IP | Deinterlacer Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Deinterlacer Intel® FPGA IP. | Video and Vision Processing Suite Intel® FPGA IP User Guide |
| Video and Image Processing | Frame Buffer II (4K Ready) Intel® FPGA IP | Video Frame Buffer Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Video Frame Buffer Intel® FPGA IP. | Video and Vision Processing Suite Intel® FPGA IP User Guide |
| Video and Image Processing | Gamma Corrector II (4K Ready) Intel® FPGA IP | 1D LUT Intel® FPGA IP | Enabled | Remove the existing IP and replace with the 1D LUT Intel® FPGA IP. | |
| Video and Image Processing | Interlacer II (4K Ready) Intel® FPGA IP | Interlacer Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Interlacer Intel® FPGA IP. | Video and Vision Processing Suite Intel® FPGA IP User Guide |
| Video and Image Processing | Mixer II (4K Ready) Intel® FPGA IP | Mixer Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Mixer Intel® FPGA IP. | Video and Vision Processing Suite Intel® FPGA IP User Guide |
| Video and Image Processing | Scaler II (4K Ready) Intel® FPGA IP | Scaler Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Scaler Intel® FPGA IP. | Video and Vision Processing Suite Intel® FPGA IP User Guide |
| Video and Image Processing | Switch II (4K Ready) Intel® FPGA IP | Switch Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Switch Intel® FPGA IP. | Video and Vision Processing Suite Intel® FPGA IP User Guide |
| Video and Image Processing | Test Pattern Generator II (4K Ready) Intel® FPGA IP | Test Pattern Generator Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Test Pattern Generator Intel® FPGA IP. | Video and Vision Processing Suite Intel® FPGA IP User Guide |
| Interface Protocols | |||||
| Audio & Video | Audio Embed Intel® FPGA IP | Not supported | N/A | Remove the existing IP. | |
| Audio & Video | Audio Extract Intel® FPGA IP | Not supported | N/A | Remove the existing IP. | |
| Audio & Video | Clocked Audio Input Intel® FPGA IP | Not supported | N/A | Remove the existing IP. | |
| Audio & Video | Clocked Audio Output Intel® FPGA IP | Not supported | N/A | Remove the existing IP. | |
| Audio & Video | DisplayPort Intel® FPGA IP | Not supported | Not enabled yet | Remove the existing IP and replace with the new IP. | |
| Audio & Video | SDI II Intel® FPGA IP | Not supported | Not enabled yet | Remove the existing IP and replace with the new IP. | |
| Ethernet/10G to 1G Multi-rate Ethernet | Ethernet 10G MAC Intel® FPGA IP | Low Latency Ethernet 10G MAC Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Low Latency Ethernet 10G MAC Intel® FPGA IP. | Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs |
| Ethernet/10G to 1G Multi-rate Ethernet | XAUI PHY IP | 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP | Enabled | Remove the existing IP and replace with the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP. | 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs |
| Ethernet/1G Multi-rate Ethernet | Triple-Speed Ethernet Intel® FPGA IP | Triple-Speed Ethernet for Intel® FPGA IP | Enabled | Remove the existing IP and regenerate the Triple-Speed Ethernet for Intel® FPGA IP. | Triple-Speed Ethernet Intel® FPGA IP User Guide |
| Ethernet/Reference Design Components | Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP | Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Ethernet Design Example Components User Guide |
| Ethernet/Reference Design Components | Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP | Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Ethernet Design Example Components User Guide |
| Ethernet/Reference Design Components | Ethernet MDIO Intel® FPGA IP | Not supported | N/A | Remove the existing IP. | |
| Ethernet/Reference Design Components | Ethernet Packet Classifier Intel® FPGA IP | Ethernet Packet Classifier Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | eCPRI Intel® FPGA IP User Guide |
| JESD | JESD204B Intel® FPGA IP | Not supported | Not enabled yet | Remove the existing IP. | |
| PCI Express | Avalon-MM Cyclone V Hard IP for PCI Express Intel® FPGA IP | GTS AXI Streaming Intel® FPGA IP for PCI Express* | Enabled | Remove the existing IP and replace with the GTS AXI Streaming Intel® FPGA IP for PCI Express* . | GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide |
| PCI Express | PHY for PCI Express (PIPE) Intel® FPGA IP | Not supported | N/A | Remove the existing IP. | |
| PCI Express | Cyclone V Hard IP for PCI Express Intel® FPGA IP | GTS AXI Streaming Intel® FPGA IP for PCI Express* | Enabled | Remove the existing IP and replace with the GTS AXI Streaming Intel® FPGA IP for PCI Express* . | GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide |
| PCI Express | PCIe Reconfig Driver Intel® FPGA IP | Not supported | N/A | Remove the existing IP. | |
| PCI Express/Example Design Components | Application Avalon-Streaming Hard IP for PCI Express* | Not supported | N/A | Remove the existing IP. | |
| Serial | 16550 Compatible UART Intel® FPGA IP | 16550 Compatible UART Intel® FPGA IP | Enabled | Remove the existing IP and regenerate 16550 Compatible UART Intel® FPGA IP. | Embedded Peripherals IP User Guide |
| Serial | Avalon I2C (Master) Intel® FPGA IP | Avalon I2C (Master) Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Embedded Peripherals IP User Guide |
| Serial | Avalon-ST Serial Peripheral Interface (SPI) Intel® FPGA IP | Avalon-ST Serial Peripheral Interface (SPI) Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Embedded Peripherals IP User Guide |
| Serial | eSPI to LPC bridge Intel® FPGA IP | eSPI to LPC bridge Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Embedded Peripherals IP User Guide |
| Serial | Intel® eSPI slave | Intel® eSPI slave | Enabled | Upgrade IP core to the latest version. | Embedded Peripherals IP User Guide |
| Serial | JTAG UART Intel® FPGA IP | JTAG UART Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Embedded Peripherals IP User Guide |
| Serial | Lightweight UART (RS-232 Serial Port) Intel® FPGA IP | Lightweight UART (RS-232 Serial Port) Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Embedded Peripherals IP User Guide |
| Serial | SPI (4 Wire Serial) Intel® FPGA IP | SPI (4 Wire Serial) Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | |
| Serial | UART (RS-232 Serial Port) Intel® FPGA IP | LWUART Intel® FPGA IP. | N/A | Remove the existing IP and replace with LWUART Intel® FPGA IP. | |
| Transceiver PHY | Transceiver PHY Reset Controller | Not supported | N/A | Remove the existing IP. The function is part of the GTS PMA/FEC Direct PHY Intel® FPGA IP. | |
| Transceiver PHY | Transceiver Reconfiguration Controller Intel® FPGA IP | Not supported | Not enabled yet | Remove the existing IP. | |
| Transceiver PHY | Transceiver Native PHY Cyclone V Intel® FPGA IP | GTS PMA/FEC Direct PHY Intel® FPGA IP | Enabled | Remove the existing IP and replace with the GTS PMA/FEC Direct PHY Intel® FPGA IP. |
FPGA GTS Transceiver PHY User Guide |
| Transceiver PHY | Custom PHY Intel® FPGA IP | GTS PMA/FEC Direct PHY Intel® FPGA IP | Enabled | Remove the existing IP and replace with the GTS PMA/FEC Direct PHY Intel® FPGA IP. |
FPGA GTS Transceiver PHY User Guide |
| Transceiver PHY | Deterministic Latency PHY Intel® FPGA IP | GTS CPRI PHY Intel® FPGA IP | Enabled | Remove the existing IP and replace with the GTS CPRI PHY Intel® FPGA IP. |
CPRI Intel® FPGA IP User Guide |
| Transceiver PHY | Cyclone V Transceiver PLL Intel® FPGA IP | Not supported | N/A | Remove the existing IP. The function is part of the GTS PMA/FEC Direct PHY Intel® FPGA IP | FPGA GTS Transceiver PHY User Guide |
| Memory Interfaces and Controllers | |||||
| Flash | Generic QUAD SPI controller II Intel® FPGA IP | Generic Serial Flash Interface Intel® FPGA IP | N/A | Remove the existing IP and replace with the Generic Serial Flash Interface Intel® FPGA IP. | Generic Serial Flash Interface Intel® FPGA IP User Guide |
| Flash | Generic QUAD SPI Controller Intel® FPGA IP | Generic Serial Flash Interface Intel® FPGA IP | N/A | Remove the existing IP and replace with the Generic Serial Flash Interface Intel® FPGA IP. | Generic Serial Flash Interface Intel® FPGA IP User Guide |
| Memory Interfaces with UniPHY | DDR2 SDRAM Controller with UniPHY Intel® FPGA IP | Not supported | N/A | Determine the memory standard that suits your application requirement, and generate the External Memory Interfaces (EMIF) IP. | External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs |
| Memory Interfaces with UniPHY | DDR3 SDRAM Controller with UniPHY Intel® FPGA IP | Not supported | N/A | Determine the memory standard that suits your application requirement, and generate the External Memory Interfaces (EMIF) IP. | External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs |
| Memory Interfaces with UniPHY | LPDDR2 SDRAM Controller with UniPHY Intel® FPGA IP | Not supported | N/A | Determine the memory standard that suits your application requirement, and generate the External Memory Interfaces (EMIF) IP. | External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs |
| Processors and Peripherals | |||||
| Co-Processors/ Nios® II Custom Instructions | Bitswap | Not supported | N/A | Remove the existing IP. | |
| Co-Processors/ Nios® II Custom Instructions | Custom Instruction Interconnect | Not supported | N/A | Remove the existing IP. Migrate to Nios® V Custom Instructions interface. | |
| Co-Processors/ Nios® II Custom Instructions | Custom Instruction Master Translator | Not supported | N/A | Remove the existing IP. Migrate to Nios® V Custom Instructions interface. | |
| Co-Processors/ Nios® II Custom Instructions | Custom Instruction Slave Translator | Not supported | N/A | Remove the existing IP. Migrate to Nios® V Custom Instructions interface. | |
| Co-Processors/ Nios® II Custom Instructions | Floating Point Hardware | Not supported | N/A | Remove the existing IP. | |
| Co-Processors/ Nios® II Custom Instructions | Floating Point Hardware 2 | Not supported | N/A | Remove the existing IP. | |
| Embedded Processors | Nios® II Processor | Nios® V/m Processor Intel® FPGA IP or Nios® V/g Processor Intel® FPGA IP | N/A | Remove the existing IP and replace with the Nios V/m Processor Intel® FPGA IP or Nios V/g Processor Intel® FPGA IP. | Nios® V Processor Reference Manual |
| Embedded Processors | Nios® V/g Processor Intel® FPGA IP | Nios® V/g Processor Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Nios® V Processor Reference Manual |
| Embedded Processors | Nios® V/m Processor Intel® FPGA IP | Nios® V/m Processor Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Nios® V Processor Reference Manual |
| Hard Processor Components | Altera HPS EMAC Interface Splitter | HPS EMAC Interface Splitter Intel® FPGA IP | Not enabled yet | Upgrade IP core to the latest version. | Embedded Peripherals IP User Guide |
| Hard Processor Components | Altera HPS Trace IP | Not supported | N/A | Remove the existing IP. | |
| Hard Processor Components | HPS GMII to RGMII Converter Intel® FPGA IP | HPS GMII to RGMII Adapter Intel® FPGA IP | Enabled | Remove the existing IP and replace with the HPS GMII to RGMII Adapter Intel® FPGA IP. | Embedded Peripherals IP User Guide |
| Hard Processor Components | HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Intel® FPGA IP | Not supported | N/A | Remove the existing IP. | |
| Hard Processor Components | MII-to-RMII Converter Intel® FPGA IP | Not supported | N/A | Remove the existing IP. | |
| Hard Processor Systems | Arria® V/ Cyclone® V Hard Processor System | Hard Processor System Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Hard Processor System Intel® FPGA IP. | Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs |
| Inter-Process Communication | Avalon Mailbox (simple) Intel® FPGA IP | Avalon Mailbox (simple) Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Embedded Peripherals IP User Guide |
| Inter-Process Communication | Avalon Mutex Intel® FPGA IP | Avalon Mutex Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Embedded Peripherals IP User Guide |
| Inter-Process Communication | Interrupt Latency Counter Intel® FPGA IP | Interrupt Latency Counter Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Embedded Peripherals IP User Guide |
| Inter-Process Communication | MSI to GIC Generator Intel® FPGA IP | MSI to GIC Generator Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Embedded Peripherals IP User Guide |
| Peripherals | I2C Slave To Avalon-MM Master Bridge Intel® FPGA IP | I2C Slave To Avalon-MM Master Bridge Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | |
| Peripherals | Interval Timer Intel® FPGA IP | Interval Timer Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Embedded Peripherals IP User Guide |
| Peripherals | Lauterbach Trace Interface IP | Trace Interface Intel® FPGA IP for Lauterbach | Enabled | Remove the existing IP and replace with the Trace Interface Intel® FPGA IP for Lauterbach. | |
| Peripherals | PIO (Parallel I/O) Intel® FPGA IP | PIO (Parallel I/O) Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Embedded Peripherals IP User Guide |
| Peripherals | Pixel Converter (BGR0 --> BGR) Intel® FPGA IP | Not supported | N/A | Remove the existing IP. | |
| Peripherals | SPI Slave to Avalon Master Bridge Intel® FPGA IP | SPI Slave to Avalon Master Bridge Intel® FPGA IP | Not enabled yet | Upgrade IP core to the latest version. | |
| Peripherals | Vectored Interrupt Controller | Vectored Interrupt Controller Intel® FPGA IP | Enabled | Remove the existing IP and replace with the Vectored Interrupt Controller Intel® FPGA IP. | Embedded Peripherals IP User Guide |
| Peripherals | Video Sync Generator Intel® FPGA IP | Not supported | N/A | Remove the existing IP. | |
| Platform Designer Interconnect | |||||
| Interrupt | Merlin IRQ Clock Crosser | Merlin IRQ Clock Crosser Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Interrupt | Merlin IRQ Fanout | Merlin IRQ Fanout Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Interrupt | Merlin IRQ Mapper | Merlin IRQ Mapper Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Memory-Mapped | AHB Slave Agent | AHB Slave Agent | Not enabled yet | Upgrade IP core to the latest version. | |
| Memory-Mapped | APB Master Agent | APB Master Agent | Not enabled yet | Upgrade IP core to the latest version. | |
| Memory-Mapped | APB Slave Agent | APB Slave Agent | Not enabled yet | Upgrade IP core to the latest version. | |
| Memory-Mapped | APB Translator | APB Translator | Not enabled yet | Upgrade IP core to the latest version. | |
| Memory-Mapped | Avalon MM Master Agent | Avalon MM Master Agent | Not enabled yet | Upgrade IP core to the latest version. | |
| Memory-Mapped | Avalon MM Master Translator | Avalon MM Master Translator | Not enabled yet | Upgrade IP core to the latest version. | |
| Memory-Mapped | Avalon MM Slave Agent | Avalon MM Slave Agent | Not enabled yet | Upgrade IP core to the latest version. | |
| Memory-Mapped | Avalon MM Slave Translator | Avalon MM Slave Translator | Not enabled yet | Upgrade IP core to the latest version. | |
| Memory-Mapped | AXI Master Network Interface (AXI Master Agent) | Not supported | N/A | Remove the existing IP. | |
| Memory-Mapped | AXI Slave Network Interface (AXI Slave Agent) | Not supported | N/A | Remove the existing IP. | |
| Memory-Mapped | AXI Translator | Not supported | N/A | Remove the existing IP. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Memory-Mapped | Error Response Slave | Error Response Slave Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Memory-Mapped | Memory Mapped Arbiter | Memory Mapped Arbiter | Not enabled yet | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Memory-Mapped | Memory Mapped Burst Adapter | Memory Mapped Burst Adapter | Not enabled yet | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Memory-Mapped | Memory-Mapped Combined sc_fifo Limiter | Memory-Mapped Combined sc_fifo Limiter Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | |
| Memory-Mapped | Memory Mapped Combined Width Adapter | Memory Mapped Combined Width Adapter | Not enabled yet | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Memory-Mapped | Memory Mapped Demultiplexer | Memory Mapped Demultiplexer | Not enabled yet | Upgrade IP core to the latest version. | HDMI Intel® FPGA IP User Guide |
| Memory-Mapped | Memory Mapped Multiplexer | Memory Mapped Multiplexer | Not enabled yet | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Memory-Mapped | Memory-Mapped Multithread Traffic Limiter | Memory-Mapped Multithread Traffic Limiter | Not enabled yet | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Memory-Mapped | Memory Mapped Router | Memory Mapped Router | Not enabled yet | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Memory-Mapped | Memory-Mapped ThreadID mapping | Memory-Mapped ThreadID Mapping Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | |
| Memory-Mapped | Memory-Mapped ThreadIDs Splitter | Memory-Mapped ThreadIDs Splitter Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | |
| Memory-Mapped | Memory Mapped Traffic Limiter | Not supported | N/A | Remove the existing IP. | |
| Memory-Mapped | Memory Mapped Width Adapter | Not supported | N/A | Remove the existing IP. | |
| Memory-Mapped Alpha | Avalon-ST Dual Clock FIFO | Not supported | N/A | Remove the existing IP. | |
| Memory-Mapped Alpha | Demultiplexer | Not supported | N/A | Remove the existing IP. | |
| Memory-Mapped Alpha | Demultiplexer | Not supported | N/A | Remove the existing IP. | |
| Memory-Mapped Alpha | Memory Mapped Router | Not supported | N/A | Remove the existing IP. | |
| Memory-Mapped Alpha | Memory Mapped Router | Not supported | N/A | Remove the existing IP. | |
| Memory-Mapped Alpha | Multiplexer | Not supported | N/A | Remove the existing IP. | |
| Tri-State Components | Conduit Pin Divider | Conduit Pin Divider Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | |
| Tri-State Components | Generic Tri-State Controller | Generic Tri-State Controller Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Tri-State Components | Tri-State Conduit Bridge | Tri-State Conduit Bridge Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Tri-State Components | |||||
| Tri-State Components | Tri-State Conduit Bridge Translator | Tri-State Conduit Bridge Translator Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |
| Tri-State Components | Tri-State Conduit Pin Sharer | Tri-State Conduit Pin Sharer Intel® FPGA IP | Enabled | Upgrade IP core to the latest version. | Quartus® Prime Pro Edition User Guide: Platform Designer |