Cyclone® V to Agilex™ 5 Device Migration Guide

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ID 787947
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Device Migration Considerations 3. Intel Quartus Prime and Platform Designer Migration Guidelines 4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide
2. Device Migration Considerations x
2.1. Device Footprint 2.2. Power Management 2.3. Configuration 2.4. Design Security Differences 2.5. Logic Elements and Embedded Memory 2.6. PLL and Clock Network 2.7. Digital Signal Processing (DSP) 2.8. I/O Interfaces 2.9. LVDS SERDES Interface 2.10. Sensor Monitoring System 2.11. MIPI D-PHY Interface 2.12. External Memory Interface (EMIF) 2.13. Hard Processor System (HPS) 2.14. Transceiver and Serial Protocols 2.15. PCIe Interface 2.16. Ethernet Interface
2.3. Configuration x
2.3.1. General Configuration Pin and Sequences 2.3.2. Device Configuration and the Secure Device Manager (SDM) 2.3.3. Active Serial (AS) Configuration 2.3.4. Avalon® -ST Configuration 2.3.5. JTAG Configuration 2.3.6. Configuration via Protocol (CvP) 2.3.7. QSPI Flash Access and Remote System Upgrade Feature 2.3.8. SEU Features 2.3.9. Configuration File Format Differences
2.8. I/O Interfaces x
2.8.1. HSIO Bank I/O Bank Architecture and Resources VCCIO and I/O Predriver Voltage Supplies I/O Types and Standards 2.8.2. HPS I/O Bank 2.8.3. SDM I/O Bank 2.8.4. HVIO Bank
2.13. Hard Processor System (HPS) x
2.13.1. HPS Boot Flows
2.14. Transceiver and Serial Protocols x
2.14.1. PMA Architecture 2.14.2. PCS Architecture 2.14.3. Transceiver Clocking 2.14.4. Transceiver Reset
3. Intel Quartus Prime and Platform Designer Migration Guidelines x
3.1. Overview 3.2. IP Comparison Between Cyclone® V and Agilex™ 5 Devices 3.3. Upgrading IP Cores and Platform Designer Systems 3.4. RTL Compliance
3.3. Upgrading IP Cores and Platform Designer Systems x
3.3.1. Upgrading IP Cores via Quartus® Prime Software Project 3.3.2. Upgrading IP Cores in Platform Designer 3.3.3. Migrating IP Cores to a Different Device
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device x
4.1. Prerequisites 4.2. Downloading and Extracting the Design Example 4.3. Migrating the Design Example
4.3. Migrating the Design Example x
4.3.1. Restoring an Archived Cyclone® V Design in the QAR Format 4.3.2. Specifying an Agilex™ 5 Device 4.3.3. Upgrading IP Cores 4.3.4. Establishing Connections 4.3.5. Compiling the Design
1. Overview
2. Device Migration Considerations
3. Intel Quartus Prime and Platform Designer Migration Guidelines
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device
A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide

2.8.1. HSIO Bank

The guidelines in this topic apply when switching your FPGA and board design from a Cyclone® V device to an Agilex™ 5 device.

I/O Bank Architecture and Resources

The FPGA I/O bank in the Cyclone® V device is row and column-oriented, with up to 10 I/O bank count per device. The On-Chip Termination (OCT) calibration block and PLL are located at the corner and center between FPGA I/O banks and can be shared across banks. For more information about Cyclone® V FPGA I/O bank orientation and shared resources, refer to the Cyclone V Device Handbook: Volume 1: Device Interfaces and Integration.

The HSIO bank in the Agilex™ 5 device is located at the top and bottom rows of the device. Each HSIO bank contains two sub-banks. Each sub-bank is further divided into four I/O lanes with 12 I/O pins per lane. Each HSIO bank has its individual PLL, clock network, OCT calibration block, and Hard Memory Controller (HMC) resources. For more information about Agilex™ 5 FPGA I/O bank orientation and shared resources, refer to the General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs .

Due to the architectural differences between Cyclone® V and Agilex™ 5 devices, the I/O design guidelines differ. When switching from the Cyclone® V FPGA I/O to Agilex™ 5 HSIO bank, you must replan your FPGA pin and resource sharing. Refer to the related information in the General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs .

VCCIO and I/O Predriver Voltage Supplies

Cyclone® V FPGA I/O bank supports a wider VCCIO range, while Agilex™ 5 HSIO bank targets a lower VCCIO supply range. The I/O pre-driver voltage supply is lowered in the Agilex™ 5 device when compared to the Cyclone® V device.

The following table lists the VCCIO and I/O pre-driver support for Agilex™ 5 and Cyclone® V devices:

Table 14.  VCCIO and I/O Pre-driver Support
Device VCCIO Support VCCPD/VCCPT
Cyclone® V 1.2 V / 1.25 V / 1.35 V / 1.5 V / 1.8 V / 2.5 V / 3.0V / 3.3V 2.5 V / 3.0 V / 3.3 V
Agilex™ 5 1.0 V / 1.05 V / 1.1 V / 1.2 V / 1.3 V 1.8 V

The VCCIO granularity for the Cyclone® V device is per bank basis, while Agilex™ 5 device is per sub-bank. You must replan your I/O standard and pin allocation per interface and the board design voltage supplies when switching from Cyclone® V FPGA I/O to Agilex™ 5 HSIO bank. Agilex™ 5 device does not support multi-volt I/O as opposed to the Cyclone® V device.

I/O Types and Standards

While the I/O types that Cyclone® V devices support are similar to the Agilex™ 5 device, the I/O standard support list differs between these two devices. The following table lists the I/O standard comparison between Cyclone® V and Agilex™ 5 devices:

Table 15.  I/O Types and Standards Comparison
I/O Types Cyclone® V I/O Standards Agilex™ 5 I/O Standards
Single-ended non-voltage referenced
  • 3.3 V LVTTL/3.3 V LVCMOS
  • 3.0 V LVTTL/3.0 V LVCMOS
  • 3.0 V PCI
  • 3.0 V PCI-X
  • 2.5 V LVCMOS
  • 1.8 V LVCMOS
  • 1.5 V LVCMOS
  • 1.2 V LVCMOS
  • 1.3 V LVCMOS
  • 1.2 V LVCMOS
  • 1.1 V LVCMOS
  • 1.05 V LVCMOS
  • 1.0 V LVCMOS
Single-ended and pseudo-differential voltage-referenced
  • SSTL-2
  • SSTL-18
  • SSTL-15
  • HSUL-12
  • 1.8 V HSTL
  • 1.5 V HSTL
  • 1.2 V HSTL
  • SSTL-12
  • HSTL-12
  • HSUL-12
  • POD12
  • POD11
  • LVSTL11
  • LVSTL105
  • LVSTL700
True differential
  • LVDS
  • RSDS
  • Mini-LVDS
  • LVPECL
  • SLVS
  • Sub-LVDS
  • HiSPi
  • True differential signaling compatible with:
    • LVDS
    • RSDS
    • SLVS
    • Mini-LVDS
    • LVPECL
  • SLVS-400
  • DPHY

Due to the differences in I/O standard support between Cyclone® V and Agilex™ 5 devices, the electrical specification and on-board termination between these devices differ. You must replan your FPGA pin assignments and board design when switching from Cyclone® V FPGA I/O to Agilex™ 5 HSIO bank to ensure that the upstream and downstream device can interface with the Agilex™ 5 HSIO bank.

Refer to the Agilex™ 5 FPGAs and SoCs Device Data Sheet for more information about the electrical specification for each I/O standard and the General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs for more information about the on-board termination recommendation.

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