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Introduction
System-Level Debugging Infrastructure
Virtual JTAG Interface Description
Run-Time Communication
Instantiating the Virtual JTAG Intel® FPGA IP Core
Simulation Support
Compiling the Design
SLD_NODE Discovery and Enumeration
Capturing the Virtual IR Instruction Register
AHDL Function Prototype
VHDL Component Declaration
VHDL LIBRARY-USE Declaration
Design Example: TAP Controller State Machine
Design Example: Modifying the DCFIFO Contents at Runtime
Design Example: Offloading Hardwired Revision Information
Document Revision History for the Virtual JTAG Intel® FPGA IP Core User Guide
Visible to Intel only — GUID: bhc1411109292871
Ixiasoft
Virtual JTAG Intel® FPGA IP Core User Guide
Updated for: |
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Intel® Quartus® Prime Design Suite 20.3 |
The Virtual JTAG Intel® FPGA IP core provides access to the PLD source through the JTAG interface. This IP core is optimized for Intel® device architectures. Using IP cores in place of coding your own logic saves valuable design time, and offers more efficient logic synthesis and device implementation. You can scale the IP core's size by setting parameters.
Section Content
Introduction
System-Level Debugging Infrastructure
Virtual JTAG Interface Description
Run-Time Communication
Instantiating the Virtual JTAG Intel FPGA IP Core
Simulation Support
Compiling the Design
SLD_NODE Discovery and Enumeration
Capturing the Virtual IR Instruction Register
AHDL Function Prototype
VHDL Component Declaration
VHDL LIBRARY-USE Declaration
Design Example: TAP Controller State Machine
Design Example: Modifying the DCFIFO Contents at Runtime
Design Example: Offloading Hardwired Revision Information
Document Revision History for the Virtual JTAG Intel FPGA IP Core User Guide
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