Cyclone® V to Agilex™ 5 Device Migration Guide

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ID 787947
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Device Migration Considerations 3. Intel Quartus Prime and Platform Designer Migration Guidelines 4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide
2. Device Migration Considerations x
2.1. Device Footprint 2.2. Power Management 2.3. Configuration 2.4. Design Security Differences 2.5. Logic Elements and Embedded Memory 2.6. PLL and Clock Network 2.7. Digital Signal Processing (DSP) 2.8. I/O Interfaces 2.9. LVDS SERDES Interface 2.10. Sensor Monitoring System 2.11. MIPI D-PHY Interface 2.12. External Memory Interface (EMIF) 2.13. Hard Processor System (HPS) 2.14. Transceiver and Serial Protocols 2.15. PCIe Interface 2.16. Ethernet Interface
2.3. Configuration x
2.3.1. General Configuration Pin and Sequences 2.3.2. Device Configuration and the Secure Device Manager (SDM) 2.3.3. Active Serial (AS) Configuration 2.3.4. Avalon® -ST Configuration 2.3.5. JTAG Configuration 2.3.6. Configuration via Protocol (CvP) 2.3.7. QSPI Flash Access and Remote System Upgrade Feature 2.3.8. SEU Features 2.3.9. Configuration File Format Differences
2.8. I/O Interfaces x
2.8.1. HSIO Bank 2.8.2. HPS I/O Bank 2.8.3. SDM I/O Bank 2.8.4. HVIO Bank
2.13. Hard Processor System (HPS) x
2.13.1. HPS Boot Flows
2.14. Transceiver and Serial Protocols x
2.14.1. PMA Architecture 2.14.2. PCS Architecture 2.14.3. Transceiver Clocking 2.14.4. Transceiver Reset
3. Intel Quartus Prime and Platform Designer Migration Guidelines x
3.1. Overview 3.2. IP Comparison Between Cyclone® V and Agilex™ 5 Devices 3.3. Upgrading IP Cores and Platform Designer Systems 3.4. RTL Compliance
3.3. Upgrading IP Cores and Platform Designer Systems x
3.3.1. Upgrading IP Cores via Quartus® Prime Software Project 3.3.2. Upgrading IP Cores in Platform Designer 3.3.3. Migrating IP Cores to a Different Device
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device x
4.1. Prerequisites 4.2. Downloading and Extracting the Design Example 4.3. Migrating the Design Example
4.3. Migrating the Design Example x
4.3.1. Restoring an Archived Cyclone® V Design in the QAR Format 4.3.2. Specifying an Agilex™ 5 Device 4.3.3. Upgrading IP Cores 4.3.4. Establishing Connections 4.3.5. Compiling the Design
1. Overview
2. Device Migration Considerations
3. Intel Quartus Prime and Platform Designer Migration Guidelines
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device
A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide

2.14.3. Transceiver Clocking

Clocking migration between Cyclone® V and Agilex™ 5 devices is not possible because of the different architectures used in both families.

In Cyclone® V, all transceiver blocks in PMA and PCS are clocked by serial or parallel clocks derived from the same clock source, which is either from the channel PLL or fractional PLL (fPLL). The channel PLL or the fPLL feeds the clock dividers in each channel, which then outputs the serial or parallel clocks to clock the datapath.

In Agilex™ 5, the architecture introduces system clocking, which differs from the transceiver clocking used in the Cyclone® V device. Between the analog PMA and the digital hard IP blocks, there is a PMA interface block. All blocks between the PMA interface blocks and the FPGA core are digital blocks (MAC, PCS, FEC, and core interface FIFO). In most cases, the system PLL clocks these digital blocks, and the PMA is clocked by its own clock (TX PLL and Clock Data Recovery (CDR) for transmitter and receiver datapath, respectively).

Figure 7. Clock Network in Agilex™ 5 Device

The following table lists the key differences between the transceiver clocking in the Cyclone® V and Agilex™ 5 device families:

Table 27.  Transceiver Clocking Comparison
Clock Cyclone® V Agilex™ 5 GTS Transceiver
Transmitter PLL

One channel PLL in every channel.

  • You can configure it as a Clock Multiplier Unit (CMU) PLL for the transmitter or as a CDR for the receiver.
  • If you configure it as a CMU PLL, you cannot use a channel receiver. To use a channel’s receiver, configure it as a CDR.

One transmit (TX) PLL in each channel.

Usage does not limit use of the transceiver channel.
Clock and Data Recovery (CDR)

One dedicated CDR in every channel.

Usage does not limit use of the transceiver channel.
Fractional PLL One fPLL for every transceiver bank. You can configure the TX PLL to run in the fractional mode.
System PLL Not available.

One in every transceiver bank.

System PLL clocks the digital blocks only. PMA is clocked by PMA clocks.

Dedicated reference clock pin One for every transceiver bank. Two for every transceiver bank.
Dual purpose RX/ reference clock pin Use one RX pin as a reference clock in every transceiver bank. Using as refclk pin disables channels receiver. Not available.

The following are additional differences:

  • Due to the difference in clock architecture between Cyclone® V and Agilex™ 5 devices, the bonding clock network is also different between Cyclone® V and Agilex™ 5 devices.
  • In Cyclone® V bonding, the clock divider of every channel receives the serial and parallel clock from the x6 or xN clock lines and feeds to the serializer directly. The following are bonded configurations in Cyclone® V:
    • Serial and parallel clocks drive x6 clock lines from the central clock divider in channel 1 and channel 4. For channels 0 to 5 within the transceiver bank, the serial and parallel clocks from x6 clock lines are distributed to every channel in both transceiver banks.
    • xN clock lines extend the clocking reach of the x6 clock line to all the channels on the same side. The clock must be on the x6 clock line and the serial and parallel clock from the x6 clock lines are distributed to every channel within the two transceiver banks. The serial and parallel clocks are then distributed beyond the two banks using the xN clock line

    Clocking modes for bonding in Agilex™ 5 are as follows:

    • System clocking (using system PLL)
    • PMA clocking (applicable only for PMA direct)

    Use the same reference clock for bonding configuration in Agilex™ 5. Use the local reference clock for x2 and x4 configurations (with four channels within a transceiver bank) and use the regional reference clock for x6 and x8 configurations.

The following table summarizes the bonding feature differences between Cyclone® V and Agilex™ 5 devices:

Table 28.  Bonding Feature Differences
Feature Cyclone® V Agilex™ 5
TX Bonding Yes Yes
Channels Up to 12 channels Up to 8 channels
Clocking mechanism Via x6 and xN clock lines
  • System PLL clocking for PMA direct (must use the same reference clock).
  • PMA clocking that is applicable for PMA direct only (must use the same reference clock).
Placement Contiguous Contiguous
Tip: For additional information, refer to the "Clocking Architecture" section of the GTS Transceiver PHY User Guide .
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