Cyclone® V to Agilex™ 5 Device Migration Guide

ID 787947
Date 4/01/2024
Public
Document Table of Contents

2.15. PCIe Interface

Agilex™ 5 offers enhanced PCIe* interface support compared to Cyclone® V. However, you cannot directly migrate a PCIe* design from a Cyclone® V device to an Agilex™ 5 device because of architectural differences and the IP used to implement the PCIe* interface.

The following table lists key differences in the PCIe* interface between Cyclone® V and Agilex™ 5 devices:

Table 30.   PCIe* Interface Differences
Feature Cyclone® V Agilex™ 5
IP Configuration Supports PCIe* endpoint and root port up to Gen2 data rate and x4 lane configuration.

Supports PCIe* endpoint, root port, and TLP bypass mode up to Gen4 data rate and x8 lane configuration.

PCIe* Interface Implementation Use either the PCIe* hard IP or PHY IP core for PCI Express* (PIPE).
  • PCIe* hard IP: Offers dedicated hard logic that includes the transaction, data link, and PHY/MAC layers.
  • PIPE mode: Implements PCS and PMA modules for up to Gen2 data rates. You must connect this PHY IP Core for PCI Express* to a third-party PHY MAC in the FPGA fabric to create a complete PCI Express* design.
Use the PCIe* hard IP only. PIPE mode is not supported.
Transceiver reconfiguration controller Connects to the PCIe* hard IP or the PIPE to compensate for the variations due to process, voltage, and temperature. Not required.
Reference clock for the PCIe* hard IP Connects to the mgmt_clk_clk signal of the transceiver reconfiguration controller. A system PLL IP is required to be connected to the PCIe* hard IP to provide the FPGA fabric clock.
Separate Reference Clock

Supports without spread spectrum.

Supports with independent spread spectrum.
PCIe* Channels Placement Follows certain placement guidelines. Constrained by the CMU PLL location and lane 0 of the PCIe* interface. You can implement independent PCIe* interface up to x4 lane width in each transceiver bank and up to x8 lane width in every two transceiver banks.

Avalon® Streaming ( Avalon® -ST) vs AXI Interface

PCIe* interface direct migration between Cyclone® V and Agilex™ 5 E Series devices is not possible because of the difference in the hard IP architecture.

Intel® recommends creating Agilex™ 5 PCIe* interface IP from scratch and not from your existing Cyclone® V design. The PCIe* hard IP application interface in the Cyclone® V device is designed based on the Avalon® -ST protocol, while Agilex™ 5 is designed based on the AXI4-Stream protocol. Hence, you must redesign the user-logic connected to the PCIe* hard IP application interface based on the AXI4-Stream protocol.