Cyclone® V to Agilex™ 5 Device Migration Guide

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ID 787947
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Device Migration Considerations 3. Intel Quartus Prime and Platform Designer Migration Guidelines 4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide
2. Device Migration Considerations x
2.1. Device Footprint 2.2. Power Management 2.3. Configuration 2.4. Design Security Differences 2.5. Logic Elements and Embedded Memory 2.6. PLL and Clock Network 2.7. Digital Signal Processing (DSP) 2.8. I/O Interfaces 2.9. LVDS SERDES Interface 2.10. Sensor Monitoring System 2.11. MIPI D-PHY Interface 2.12. External Memory Interface (EMIF) 2.13. Hard Processor System (HPS) 2.14. Transceiver and Serial Protocols 2.15. PCIe Interface 2.16. Ethernet Interface
2.3. Configuration x
2.3.1. General Configuration Pin and Sequences 2.3.2. Device Configuration and the Secure Device Manager (SDM) 2.3.3. Active Serial (AS) Configuration 2.3.4. Avalon® -ST Configuration 2.3.5. JTAG Configuration 2.3.6. Configuration via Protocol (CvP) 2.3.7. QSPI Flash Access and Remote System Upgrade Feature 2.3.8. SEU Features 2.3.9. Configuration File Format Differences
2.8. I/O Interfaces x
2.8.1. HSIO Bank 2.8.2. HPS I/O Bank 2.8.3. SDM I/O Bank 2.8.4. HVIO Bank
2.13. Hard Processor System (HPS) x
2.13.1. HPS Boot Flows
2.14. Transceiver and Serial Protocols x
2.14.1. PMA Architecture 2.14.2. PCS Architecture 2.14.3. Transceiver Clocking 2.14.4. Transceiver Reset
3. Intel Quartus Prime and Platform Designer Migration Guidelines x
3.1. Overview 3.2. IP Comparison Between Cyclone® V and Agilex™ 5 Devices 3.3. Upgrading IP Cores and Platform Designer Systems 3.4. RTL Compliance
3.3. Upgrading IP Cores and Platform Designer Systems x
3.3.1. Upgrading IP Cores via Quartus® Prime Software Project 3.3.2. Upgrading IP Cores in Platform Designer 3.3.3. Migrating IP Cores to a Different Device
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device x
4.1. Prerequisites 4.2. Downloading and Extracting the Design Example 4.3. Migrating the Design Example
4.3. Migrating the Design Example x
4.3.1. Restoring an Archived Cyclone® V Design in the QAR Format 4.3.2. Specifying an Agilex™ 5 Device 4.3.3. Upgrading IP Cores 4.3.4. Establishing Connections 4.3.5. Compiling the Design
1. Overview
2. Device Migration Considerations
3. Intel Quartus Prime and Platform Designer Migration Guidelines
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device
A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide

4.3.4. Establishing Connections

After parameterizing the IPs, you might observe several messages, errors, and warnings in the System Messages tab. You can resolve these messages by establishing proper connections.
  1. Establish proper connections by right-clicking on the component, selecting Connections, and choosing options based on the following table:
    From To
    clk
    clk.out_clk reset.clk
    clk.out_clk new_pll.refclk
    reset
    reset.out_reset new_pll.reset
    reset.out_reset niosv.reset
    reset.out_reset new_ocm.reset1
    new_pll
    new_pll.outclk0 niosv.clk
    new_pll.outclk0 sysid.clk
    new_pll.outclk0 new_ocm.clk1
    new_pll.outclk0 led.clk
    new_pll.outclk0 jtag.clk
    niosv
    niosv.instruction_manager new_ocm.s1
    niosv.data_manager new_ocm.s1
    niosv.data_manager sysid.control_slave
    niosv.data_manager led.s1
    niosv.data_manager jtag.avalon_jtag_slave
    niosv.platform_irq_rx jtag.irq
    resetrelease
    resetrelease.ninit_done niosv.reset
  2. Sync all system information by clicking Sync System Infos.
  3. For niosv, in the Parameters > Vectors tab, set Reset Agent to new_ocm.s1. This can only be done after making the connections.
  4. Remove the overlapping address error by clicking System > Assign Base Addresses. System Messages must be clear of any messages by this point.
  5. Click File > Save.
  6. Click Generate > Generate HDL.
    1. Under Synthesis, uncheck Create block symbol file (.bsf) and Generate IP core Documentation options.
    2. Under Simulation, select Verilog for Create Simulation Model and check ModelSim.
    Figure 29. Generation Dialog
  7. Click Generate. Once generation is complete, click Close.
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