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2.1. Device Footprint
2.2. Power Management
2.3. Configuration
2.4. Design Security Differences
2.5. Logic Elements and Embedded Memory
2.6. PLL and Clock Network
2.7. Digital Signal Processing (DSP)
2.8. I/O Interfaces
2.9. LVDS SERDES Interface
2.10. Sensor Monitoring System
2.11. MIPI D-PHY Interface
2.12. External Memory Interface (EMIF)
2.13. Hard Processor System (HPS)
2.14. Transceiver and Serial Protocols
2.15. PCIe Interface
2.16. Ethernet Interface
2.3.1. General Configuration Pin and Sequences
2.3.2. Device Configuration and the Secure Device Manager (SDM)
2.3.3. Active Serial (AS) Configuration
2.3.4. Avalon® -ST Configuration
2.3.5. JTAG Configuration
2.3.6. Configuration via Protocol (CvP)
2.3.7. QSPI Flash Access and Remote System Upgrade Feature
2.3.8. SEU Features
2.3.9. Configuration File Format Differences
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4.1. Prerequisites
| Cyclone V OPN used | 5CGXFC5C6F27C7 |
Before using the design example, ensure you have completed the following:
- Installed the latest Quartus® Prime Pro Edition software version with Agilex™ 5 device support.
- Downloaded and extracted the supporting design example files as described in Downloading and Extracting the Design Example.
- Developed basic familiarity with the Quartus® Prime Pro Edition FPGA implementation flow and the Platform Designer tool.