ID
813667
Date
7/08/2024
Public
Visible to Intel only — GUID: zbe1708649076403
Ixiasoft
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices
2. Getting Started
3. Functional Description
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP
5. Interface Signals
6. Configuration Registers
7. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives
8. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
5.1. Clock Signals
5.2. Reset Signals
5.3. Serial Interface Signals
5.4. Avalon Memory-Mapped Interface Signals
5.5. XGMII Signals
5.6. GMII Signals
5.7. PHY Status Signals
5.8. Transceiver Mode and Operating Speed Signals
5.9. Transceiver Status and Reconfiguration Signals
5.10. GTS Reset Sequencer Signals
5.11. Dynamic Reconfiguration SRC Signals
Visible to Intel only — GUID: zbe1708649076403
Ixiasoft
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices
Updated for: |
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Intel® Quartus® Prime Design Suite 24.2 |
IP Version 3.0.0 |
The 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 devices implements the Ethernet protocol as defined in the IEEE 802.3 2018 standard. It consists of a physical coding sublayer (PCS) and an embedded physical media attachment (PMA). The IP leverages GTS Ethernet Hard IP transceiver for serial transmission with soft logic added to implement interface to MAC.
Note: Device support for Agilex™ 5 D-Series FPGAs and SoCs in the Quartus® Prime Pro Edition software version 24.2 is restricted. To enable D-Series device support in your instance of the Quartus® Prime Pro Edition software, contact your regional Altera sales representative.