Cyclone® V to Agilex™ 5 Device Migration Guide

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ID 787947
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Device Migration Considerations 3. Intel Quartus Prime and Platform Designer Migration Guidelines 4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide
2. Device Migration Considerations x
2.1. Device Footprint 2.2. Power Management 2.3. Configuration 2.4. Design Security Differences 2.5. Logic Elements and Embedded Memory 2.6. PLL and Clock Network 2.7. Digital Signal Processing (DSP) 2.8. I/O Interfaces 2.9. LVDS SERDES Interface 2.10. Sensor Monitoring System 2.11. MIPI D-PHY Interface 2.12. External Memory Interface (EMIF) 2.13. Hard Processor System (HPS) 2.14. Transceiver and Serial Protocols 2.15. PCIe Interface 2.16. Ethernet Interface
2.3. Configuration x
2.3.1. General Configuration Pin and Sequences 2.3.2. Device Configuration and the Secure Device Manager (SDM) 2.3.3. Active Serial (AS) Configuration 2.3.4. Avalon® -ST Configuration 2.3.5. JTAG Configuration 2.3.6. Configuration via Protocol (CvP) 2.3.7. QSPI Flash Access and Remote System Upgrade Feature 2.3.8. SEU Features 2.3.9. Configuration File Format Differences
2.8. I/O Interfaces x
2.8.1. HSIO Bank 2.8.2. HPS I/O Bank 2.8.3. SDM I/O Bank 2.8.4. HVIO Bank
2.13. Hard Processor System (HPS) x
2.13.1. HPS Boot Flows
2.14. Transceiver and Serial Protocols x
2.14.1. PMA Architecture 2.14.2. PCS Architecture 2.14.3. Transceiver Clocking 2.14.4. Transceiver Reset
3. Intel Quartus Prime and Platform Designer Migration Guidelines x
3.1. Overview 3.2. IP Comparison Between Cyclone® V and Agilex™ 5 Devices 3.3. Upgrading IP Cores and Platform Designer Systems 3.4. RTL Compliance
3.3. Upgrading IP Cores and Platform Designer Systems x
3.3.1. Upgrading IP Cores via Quartus® Prime Software Project 3.3.2. Upgrading IP Cores in Platform Designer 3.3.3. Migrating IP Cores to a Different Device
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device x
4.1. Prerequisites 4.2. Downloading and Extracting the Design Example 4.3. Migrating the Design Example
4.3. Migrating the Design Example x
4.3.1. Restoring an Archived Cyclone® V Design in the QAR Format 4.3.2. Specifying an Agilex™ 5 Device 4.3.3. Upgrading IP Cores 4.3.4. Establishing Connections 4.3.5. Compiling the Design
1. Overview
2. Device Migration Considerations
3. Intel Quartus Prime and Platform Designer Migration Guidelines
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device
A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide

2.2. Power Management

Power Rails

Cyclone® V series offer fixed-voltage option.

Agilex™ 5 devices offer the following options:

  • SmartVID voltage option: Available in D-series and E-series (Group A) devices with power option code “-V.” Devices operate at the optimum-core voltage that meets the VID power limit and requires device performance for various FPGA applications. The dynamic voltage supply is necessary for VCC and VCCP using the PMBus-compliant voltage regulator. The SmartVID feature compensates for process variation by narrowing the process distribution using voltage adaptation. The SmartVID feature allows a power regulator to provide the Agilex™ 5 E-series devices with VCC and VCCP voltage levels that maintain the performance of the specific device speed grade.
  • Fixed-voltage option: Available only in E-series (Group B) devices with option code “-S" or "-X.” Devices supply fixed voltage to VCC and VCCP.
Note:
  • Since the Cyclone® V device does not support SmartVID feature, migrating from a Cyclone® V device to Agilex™ 5 device with VID options is not supported due to architectural differences.
  • In terms of power rails, there are differences between Cyclone® V and Agilex™ 5 devices, so you cannot migrate most of the power rails from a Cyclone® V device to Agilex™ 5.

The following table lists all power rails for Cyclone® V and Agilex™ 5 devices:

Table 1.  Power Rail Groups of Cyclone® V and Agilex™ 5 Devices
Cyclone® V Agilex™ 5
Group 1 Group 2 Group 1 Group 2A Group 2B

VCC

VCCE_GXB

VCCL_GXB

VCC_HPS

VCCPGM

VCCIO

VCCPD VCCA_FPLL

VCCH_GXB

VCC_AUX

VCCPD_HPS

VCCIO_HPS

VCCRSTCLK_HPS

VCCPLL_HPS

VCC_AUX_SHARED

VCC

VCCP

VCCL_ADC_SDM

VCC_IO_SDM

VCCH_SDM

VCCL_SDM

VCCPLLDIG_SDM

VCCL_HPS

V CCL_HPS_CORE0_CORE1

VCCL_HPS_CORE2

VCCL_HPS_CORE3

VCCPLLDIG1_HPS

VCCPLLDIG2_HPS

VCC_HSSI_[L1,R4]

VCCERT_GTS[L1,R4][A,B,C,D]

VCCPT_HVIO

VCCFUSEWR_SDM

VCCIO_SDM

VCCIO_HPS

VCCPLL1_HPS

VCCPLL2_HPS

VCCEHT_GTS [L1,R4] [A,B,C,D]

VCCPT

VCCPLL_SDM

VCCADC

VCCIO_PIO

VCCIO_HVIO(1.8V)

VCCIO_PIO_SDM

VCCRCORE

For more information about device specification and requirements, refer to the Agilex™ 5 FPGAs and SoCs Device Data Sheet and Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs .

Power Sequence Recommendations

Cyclone® V and Agilex™ 5 have different power sequence recommendations.

In the Power Rails Groups table, the Cyclone® V device supports two power groups, where Group 1 must ramp up to a minimum of 80% of its full rail before Group 2 starts to ramp up.

For Agilex™ 5 device, all power rails in Group 1 must ramp up (in any order) to a minimum of 90% of its respective nominal voltage before the power rails from Group 2A can start ramping up. The power rails within Group 2A can ramp up in any order after the last power rail in Group 1 ramps to the minimum threshold of 90% of its nominal voltage. All power rails in Group 2A must ramp up to a minimum threshold of 90% of its nominal value before the Group 2B power rails can start ramping up. The power rails within Group 2B can ramp up in any order after the last power rail in Group 2A ramps up to a minimum threshold of 90% of their full value.

Cyclone® V devices support the hot socketing feature, also known as hot plug-in or hot swap. This feature allows you to drive signals into the I/O pin before or during power-up or power-down without damaging the device.

Agilex™ 5 devices do not support the hot socketing feature. You must adhere to the design guidelines on I/O pin voltage and current limit for unpowered, power-up, and power-down device states.

For more information, refer to the Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration, Power Management User Guide: Agilex™ 5 FPGAs and SoCs , and General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs .

Power Estimation

Cyclone® V and Agilex™ 5 have different power models due to their architecture.

Perform power estimation in the following manner:
  • Cyclone® V device: Use the Early Power Estimator (EPE). For more information, refer to the Early Power Estimator User Guide
  • Agilex™ 5 device: Use the Power and Thermal Calculator (PTC). For more information, refer to Intel® FPGA Power and Thermal Calculator User Guide.
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