Cyclone® V to Agilex™ 5 Device Migration Guide

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ID 787947
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Device Migration Considerations 3. Intel Quartus Prime and Platform Designer Migration Guidelines 4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide
2. Device Migration Considerations x
2.1. Device Footprint 2.2. Power Management 2.3. Configuration 2.4. Design Security Differences 2.5. Logic Elements and Embedded Memory 2.6. PLL and Clock Network 2.7. Digital Signal Processing (DSP) 2.8. I/O Interfaces 2.9. LVDS SERDES Interface 2.10. Sensor Monitoring System 2.11. MIPI D-PHY Interface 2.12. External Memory Interface (EMIF) 2.13. Hard Processor System (HPS) 2.14. Transceiver and Serial Protocols 2.15. PCIe Interface 2.16. Ethernet Interface
2.3. Configuration x
2.3.1. General Configuration Pin and Sequences Configuration Pin Differences 2.3.2. Device Configuration and the Secure Device Manager (SDM) 2.3.3. Active Serial (AS) Configuration 2.3.4. Avalon® -ST Configuration 2.3.5. JTAG Configuration 2.3.6. Configuration via Protocol (CvP) 2.3.7. QSPI Flash Access and Remote System Upgrade Feature 2.3.8. SEU Features 2.3.9. Configuration File Format Differences
2.8. I/O Interfaces x
2.8.1. HSIO Bank 2.8.2. HPS I/O Bank 2.8.3. SDM I/O Bank 2.8.4. HVIO Bank
2.13. Hard Processor System (HPS) x
2.13.1. HPS Boot Flows
2.14. Transceiver and Serial Protocols x
2.14.1. PMA Architecture 2.14.2. PCS Architecture 2.14.3. Transceiver Clocking 2.14.4. Transceiver Reset
3. Intel Quartus Prime and Platform Designer Migration Guidelines x
3.1. Overview 3.2. IP Comparison Between Cyclone® V and Agilex™ 5 Devices 3.3. Upgrading IP Cores and Platform Designer Systems 3.4. RTL Compliance
3.3. Upgrading IP Cores and Platform Designer Systems x
3.3.1. Upgrading IP Cores via Quartus® Prime Software Project 3.3.2. Upgrading IP Cores in Platform Designer 3.3.3. Migrating IP Cores to a Different Device
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device x
4.1. Prerequisites 4.2. Downloading and Extracting the Design Example 4.3. Migrating the Design Example
4.3. Migrating the Design Example x
4.3.1. Restoring an Archived Cyclone® V Design in the QAR Format 4.3.2. Specifying an Agilex™ 5 Device 4.3.3. Upgrading IP Cores 4.3.4. Establishing Connections 4.3.5. Compiling the Design
1. Overview
2. Device Migration Considerations
3. Intel Quartus Prime and Platform Designer Migration Guidelines
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device
A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide

2.3.1. General Configuration Pin and Sequences

This topic describes key differences in general configuration pin sequences between Cyclone® V and Agilex™ 5 devices.

Configuration Pin Differences

Agilex™ 5 device configuration pin behavior differs from the Cyclone® V device. Knowing these differences and how these pins behave helps when migrating the Cyclone® V configuration solution to Agilex™ 5 device and debugging configuration issues.

The following table lists general configuration pin differences between Cyclone® V and Agilex™ 5 devices:

Table 3.  General Configuration Pin Differences
General Configuration Pin Name in Cyclone® V Device General Configuration Pin Name in Agilex™ 5 Device Notes for Agilex™ 5 Device
CLKUSR OSC_CLK_1 An external clock source you can supply to increase the configuration throughput. Supported frequencies are 25MHz, 100MHz, and 125MHz. Refer to the "Setting Configuration Clock Source" topic in the Agilex™ 5 Configuration User Guide for instructions on setting the clock source and frequency in the Quartus® Prime Pro Edition software.
MSEL[0] SDM_IO5(MSEL[0]) Use 4.7 kΩ resistors to pull the MSEL[2:0] pins up to VCCIO_SDM or down to the ground as per the MSEL[2:0] pins setting requirement for your configuration scheme.
MSEL[1] SDM_IO7(MSEL[1])
MSEL[2] SDM_IO9(MSEL[2])
nSTATUS nSTATUS No longer open drain. Intel® recommends a 10 kΩ pull up to VCCIO_SDM.
nCONFIG nCONFIG  
CONF_DONE SDM_IO5, SDM_IO16 (CONF_DONE) No single dedicated pin location. No longer open-drain. External pull-up is not mandatory.
INIT_DONE SDM_IO0, SDM_IO16(INIT_DONE) No single dedicated pin location. No longer open drain. External pull-up is not mandatory.
nCE N/A Does not support multidevice configuration.
nCEO N/A Does not support multidevice configuration.
nIO_PULLUP N/A Not supported.
DEV_OE N/A Does not support enable device-wide output enable (DEV_OE).
DEV_CLRn N/A Does not support enable device-wide reset (DEV_CLRn).

The following are other key differences to consider:

  • You must use the Reset Release Intel® FPGA IP in the Agilex™ 5 device to hold your design in reset until it is configured and the entire FPGA fabric has entered the user mode, and to avoid intermittent functional issues.
  • You must replace the Reset Release Intel® FPGA IP (s10_user_rst_clkgate) with Reset Release Intel® FPGA IP (intel_user_rst_clkgate) in your design. For more information about Agilex™ 5 Reset Release IP, refer to the Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs.
  • Consider the following configuration and reconfiguration sequence:
    • SDM device: After the device powers on and exits power-on reset, during Secure Device Manager (SDM) startup stage, the SDM runs the firmware stored in the on-chip boot ROM and enters the idle state until the host drives nCONFIG high. The host must not drive nCONFIG high before all clocks are stable.
    • FPGA configuration: In an Agilex™ 5 device, the initial part of the configuration bitstream consists of firmware section loaded initially followed by I/O, Hard Processor System First Stage Boot Loader (HPS FSBL), and core configuration data.
    • FPGA reconfiguration: For reconfiguration triggered by a pulse of nCONFIG low, the SDM checks the updated firmware and compares it with the existing firmware. The SDM continues with the configuration flow if both firmware is the same. If the firmware differs, the SDM transitions to the firmware that comes with the bitstream.

For additional information, refer to the configuration sequence flow chart or state diagram in the Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration and Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs.

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