Advanced SEU Detection Intel® FPGA IP User Guide

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ID 683542
Date 11/11/2024
Public
Document Table of Contents
Document Table of Contents x
1. Advanced SEU Detection Intel® FPGA IP Overview 2. Advanced SEU Detection Intel® FPGA IP Functional Description 3. Using the Advanced SEU Detection Intel® FPGA IP 4. SEU Mitigation on CRAM Array 5. Advanced SEU Detection Intel® FPGA IP User Guide Archives 6. Document Revision History for the Advanced SEU Detection Intel® FPGA IP User Guide
2. Advanced SEU Detection Intel® FPGA IP Functional Description x
2.1. On-Chip Lookup Sensitivity Processing 2.2. Off-Chip Lookup Sensitivity Processing
2.1. On-Chip Lookup Sensitivity Processing x
2.1.1. On-Chip Sensitivity Processor 2.1.2. On-Chip Processing Signals
2.2. Off-Chip Lookup Sensitivity Processing x
2.2.1. Off-Chip Lookup Sensitivity Processing Operation Flow 2.2.2. External Sensitivity Processor 2.2.3. Off-Chip Processing Signals 2.2.4. SMH Lookup
2.2.4. SMH Lookup x
2.2.4.1. SMH File Types
3. Using the Advanced SEU Detection Intel® FPGA IP x
3.1. Customizing and Generating IP Cores 3.2. Advanced SEU Detection IP Core Parameters
3.1. Customizing and Generating IP Cores x
3.1.1. IP Catalog and Parameter Editor 3.1.2. The Parameter Editor 3.1.3. Specifying IP Core Parameters and Options
3.1.3. Specifying IP Core Parameters and Options x
3.1.3.1. IP Core Generation Output ( Quartus® Prime Pro Edition)
4. SEU Mitigation on CRAM Array x
4.1. Enabling the Advanced SEU Detection Feature in the Quartus® Prime Software 4.2. Hierarchy Tagging 4.3. Sensitivity Map Header File Lookup
4.2. Hierarchy Tagging x
4.2.1. Using Partitions to Specify Logic Sensitivity ID
4.3. Sensitivity Map Header File Lookup x
4.3.1. Programming Sensitivity Map Header File into Memory 4.3.2. Performing a Lookup for SMH Revision 1 ( Stratix® IV and Arria® II) 4.3.3. Performing a Lookup for SMH Revision 2 ( Stratix® V, Arria® V, and Cyclone® V Devices) 4.3.4. Performing a Lookup for SMH Revision 3 ( Arria® 10 and Cyclone® 10 GX Devices)
1. Advanced SEU Detection Intel® FPGA IP Overview
2. Advanced SEU Detection Intel® FPGA IP Functional Description
3. Using the Advanced SEU Detection Intel® FPGA IP
4. SEU Mitigation on CRAM Array
5. Advanced SEU Detection Intel® FPGA IP User Guide Archives
6. Document Revision History for the Advanced SEU Detection Intel® FPGA IP User Guide

1. Advanced SEU Detection Intel® FPGA IP Overview

Updated for:
Intel® Quartus® Prime Design Suite 18.1

The Advanced SEU Detection IP core enables you to perform:

  • Hierarchy tagging—Allows you to describe the criticality of each portion of your design's hierarchy relative to single event upset (SEU). You perform hierarchy tagging during the design phase.
  • Sensitivity processing—Determines the criticality of an SEU detected and located by error detection cyclical redundancy check (EDCRC) hard IP. This feature includes on- and off-chip sensitivity processing. The system performs sensitivity processing at runtime.
Table 1.  Features Device Family Support
Feature Supported Devices
Hierarchy Tagging and Sensitivity Processing Arria® 10, Cyclone® 10 GX, Stratix® V, Arria® V, and Cyclone® V.
Sensitivity Processing Stratix® IV, Arria® II GX, and Arria® II GZ.

You can select and configure the Advanced SEU Detection IP core through the IP Catalog and parameter editor in the Quartus® Prime software.

The Advanced SEU Detection IP core must be used along with the EMR Unloader Intel® FPGA IP core. The EMR Unloader IP core provides Error Message Register (EMR) contents whenever it detects an EDCRC error. Connect the emr, emr_valid and emr_error signals from your EMR Unloader IP variation to the corresponding inputs of your Advanced SEU Detection variation.

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