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1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP
3. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP
4. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs
5. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
6. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide
3.5.6.4.1. Timing Closure: Dynamic Reconfiguration
3.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
3.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
3.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
3.5.6.4.5. I/O Timing Violation
3.5.6.4.6. Internal FPGA Path Timing Violation
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration
4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
4.5.6.4.5. I/O Timing Violation
4.5.6.4.6. Internal FPGA Path Timing Violation
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2.2. Functional Description
The PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP utilizes the I/O banks in Intel® Agilex™ devices. Each I/O bank has two I/O sub-banks in each device. The top sub-bank is placed near the edge of the die, and the bottom sub-bank is placed near the FPGA core.
Each each sub-bank contains the following components:
- Hard memory controller
- I/O PLL and PHY clock trees
- DLL
- Input DQS/strobe trees
- 48 pins, organized into four I/O lanes of 12 pins each
Figure 1. Intel® Agilex™ I/O Bank Structure