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1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP
3. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP
4. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs
5. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
6. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide
3.5.6.4.1. Timing Closure: Dynamic Reconfiguration
3.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
3.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
3.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
3.5.6.4.5. I/O Timing Violation
3.5.6.4.6. Internal FPGA Path Timing Violation
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration
4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
4.5.6.4.5. I/O Timing Violation
4.5.6.4.6. Internal FPGA Path Timing Violation
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2.2.3.3. Input Path
The input path of the IP consists of a data path, a strobe path, and a read enable path as shown in the following figure.
Figure 11. Input Path
Path | Description |
---|---|
Data Path | Receives data from external device to the FPGA core logic.
The data path consists of a PVT compensated delay chain, a DDIO and a read FIFO.
Signals used in this path are:
The IP supports SDR input by sending data on single clock cycle from the external device. |
Strobe Path | Input strobe (dqs) to capture input data from external device.
The strobe path consists of pstamble_reg (a gating component) and a PVT compensated delay chain.
Signals used in this path are:
|
Read and Strobe Enable Path | Generates control signals for strobe calibration and reading data from Read FIFO.
The read and strobe enable path consists of VFIFO, DQS_EN FIFO, and an interpolator.
Signals used in this path are:
|
Read Operation Sequence Number | Operation |
---|---|
1 | The core asserts the rdata_en signal to the PHY Lite for Parallel Interfaces IP and issues a read command to the external device. |
2 | VFIFO and DQS_EN FIFO generate the dqs_enable signal to pstamble_reg. This signal is delayed by the programmed read latency (which should match the latency of the external device). |
3 | The pstamble_reg generates dqs_clean signal as valid data enters the read path. |
4 | The Delay Chain (PVT) adjusts the strobe with phase offset between the strobe and the input data (for example, 90° phase shift for DDR center-alignment). |
5 | The dqs signal is then used as strobe to read data from external device into the DDIO and Read FIFO modules. |
6 | The VFIFO asserts the read_enable signal to Read FIFO and the rdata_valid signal to the core simultaneously. The PHY Lite for Parallel Interfaces IP sends the captured data to the core with the associated valid signal. |
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