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1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP
3. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP
4. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs
5. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
6. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide
3.5.6.4.1. Timing Closure: Dynamic Reconfiguration
3.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
3.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
3.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
3.5.6.4.5. I/O Timing Violation
3.5.6.4.6. Internal FPGA Path Timing Violation
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration
4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
4.5.6.4.5. I/O Timing Violation
4.5.6.4.6. Internal FPGA Path Timing Violation
Visible to Intel only — GUID: bhc1410942177186
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6. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide
Document Version | Intel® Quartus® Prime Version | Changes |
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2021.09.01 | 21.1 | Removed unsupported VREF modes from the VREF_MODE Description table for the PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP: VCCIO_45, VCCIO_50, VCCIO_55, VCCIO_65, VCCIO_70, VCCIO_75. |
2021.07.16 | 21.1 |
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2021.02.04 | 20.4 | Updated the PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP v20.3.0 as follows:
Updated the Guidelines: Group Pin Placement sections for the following IPs:
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Document Version | Intel® Quartus® Prime Version | Changes |
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2020.11.13 | 20.3 |
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2020.10.19 | 20.3 |
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2020.06.30 | 20.2 | Updated the Intel® Stratix® 10 I/O Bank Structure figure showing the I/O bank structure:
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Document Version | Intel® Quartus® Prime Version | IP Version | Changes |
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2020.02.24 | 19.3 | 19.1 |
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2019.12.16 | 19.3 | 19.1 |
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2019.11.07 | 19.3 | 19.1 |
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2019.04.04 | 19.1 | 19.1 |
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2019.04.01 | 19.1 | 19.1 |
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2019.01.09 | 18.1 | 18.1 | Added estimation time for a delay register value to change in Reconfiguration Features and Register Addressing. |
2018.09.21 | 18.1 | 18.1 |
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2018.06.06 | 18.0 | 18.0 |
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2018.05.07 | 18.0 | 18.0 |
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Date | Version | Changes |
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November 2017 | 2017.11.30 |
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June 2017 | 2017.06.16 |
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February 2017 | 2017.02.24 |
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October 2016 | 2016.10.28 |
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May 2016 | 2016.05.02 |
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December 2015 | 2015.12.11 |
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November 2015 | 2015.11.02 |
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June 2015 | 2015.06.12 |
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January 2015 | 2015.01.28 | Updated related information link to Functional Description for External Memory Interfaces in Arria 10 Devices. |
December, 2014 | 2014.12.30 |
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August, 2014 |
2014.08.18 |
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November, 2013 |
2013.11.29 |
Initial release. |