Visible to Intel only — GUID: zeb1599634275039
Ixiasoft
Visible to Intel only — GUID: zeb1599634275039
Ixiasoft
2.3.2.2. Output Path Signals
Signal Name | Direction | Width | Description |
---|---|---|---|
group_oe_from_core | Input | Quarter-rate: 4 |
Output enable signal from FPGA core. Synchronous to the core_clk_out output from the IP. This signal is shared across all groups. |
group_<n>_data_from_core | Input | Quarter rate-DDR: 8 x PIN_WIDTH Quarter-rate SDR: 4 x PIN_WIDTH |
Data signal from Intel FPGA core. Synchronous to the core_clk_out output from the IP. |
group_strobe_out_en | Input | Quarter-rate: 4 |
Strobe output enable from FPGA core. Synchronous to the core_clk_out output from the IP. This signal is shared across all groups. |
group_<n>_data_out /group_<n>_data_io | Output/Bidirectional | 1 to 34 | Data output from the IP. Synchronous to the group_<n>_strobe_out or group_<n>_strobe_io output from the IP. If the Pin Type parameter is set to Output, the group_<n>_data_out signals are used. If the Pin Type parameter is set to Bidirectional, the group_<n>_data_io signals are used. |
group_<n>_strobe_out/group_strobe_io/group_<n>_strobe_io | Output/Bidirectional | 1 | Positive output strobe from the IP. If the Pin Type is set to Output, the group_<n>_strobe_out signal is used. If the Pin Type is set to Bidirectional the group_<n>_strobe_io signal is used. |
group_<n>_strobe_out_n /group_<n>_strobe_io_n | Output/Bidirectional | 1 | Negative output strobe fro the IP. This is used if the Strobe Configuration is set to Differential. If the Pin Type is set to Output, the group_<n>_strobe_out_n signal is used. If the Pin Type is set to Bidirectional, the group_<n>_strobe_io_n signal is used. |