PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 9/01/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.5.2. Reference Clock

You are recommended to source the reference clock to the PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP from a dedicated clock pin. Use the clock pin in the I/O sub-bank with the following command:
set_location_assignment <PIN_NUMBER> -to <pll_ref_clock_signal_name>