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1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP
3. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP
4. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs
5. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
6. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide
3.5.6.4.1. Timing Closure: Dynamic Reconfiguration
3.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
3.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
3.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
3.5.6.4.5. I/O Timing Violation
3.5.6.4.6. Internal FPGA Path Timing Violation
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration
4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
4.5.6.4.5. I/O Timing Violation
4.5.6.4.6. Internal FPGA Path Timing Violation
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2.2.5. I/O Timing
You are advised to design the system with the worst case losses for the PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP.
Data Flow Direction | Applies to PHY Lite for Parallel Interfaces IP Mode | Worst Case Losses4 |
---|---|---|
Driving (PHY Lite for Parallel Interfaces IP is driving the I/Os) | Output / bi-directional | 45% UI |
Receiving (PHY Lite for Parallel Interfaces IP is sampling the I/Os) | Input / bi-directional | POD 1.2 V: 38% UI SSTL 1.2 V: 49% UI |
4 The losses are denoted for a PHY Lite for Parallel Interfaces IP operating at 1,200 MHZ at DDR.