PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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Date 9/01/2021
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Document Table of Contents
Document Table of Contents x
1. About the PHY Lite for Parallel Interfaces IP 2. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP 3. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP 4. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs 5. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives 6. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide
1. About the PHY Lite for Parallel Interfaces IP x
1.1. Device Family Support 1.2. Features
2. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP x
2.1. Release Information 2.2. Functional Description 2.3. Getting Started 2.4. I/O Standards 2.5. Design Guidelines 2.6. Design Example
2.2. Functional Description x
2.2.1. Intel® Agilex™ I/O Sub-bank Interconnects 2.2.2. Intel® Agilex™ Input DQS/Strobe Tree 2.2.3. PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP Top Level Interfaces 2.2.4. Dynamic Reconfiguration 2.2.5. I/O Timing
2.2.3. PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP Top Level Interfaces x
2.2.3.1. Clocks 2.2.3.2. Output Path 2.2.3.3. Input Path
2.2.3.1. Clocks x
2.2.3.1.1. Clock Frequency Relationships
2.2.3.2. Output Path x
2.2.3.2.1. Output Path Data Alignment
2.2.3.3. Input Path x
2.2.3.3.1. Input Path Data Alignment
2.2.4. Dynamic Reconfiguration x
2.2.4.1. Connectivity 2.2.4.2. Reconfiguration Features and Register Addressing 2.2.4.3. Dynamic Reconfiguration Guidelines
2.2.4.2. Reconfiguration Features and Register Addressing x
2.2.4.2.1. Control Registers Addresses 2.2.4.2.2. Control Registers
2.2.4.3. Dynamic Reconfiguration Guidelines x
2.2.4.3.1. Strobe Enable Window Calibration 2.2.4.3.2. Output and Strobe Enable Minimum and Maximum Phase Settings 2.2.4.3.3. Input DQ/DQS Delay Chains Maximum Values
2.3. Getting Started x
2.3.1. Parameter Settings 2.3.2. Signals
2.3.1. Parameter Settings x
2.3.1.1. Read Latency 2.3.1.2. Write Latency
2.3.2. Signals x
2.3.2.1. Clock and Reset Interface Signals 2.3.2.2. Output Path Signals 2.3.2.3. Input Path Signals
2.4. I/O Standards x
2.4.1. Input Buffer Reference Voltage (VREF) 2.4.2. On-Chip Termination (OCT)
2.4.2. On-Chip Termination (OCT) x
2.4.2.1. RZQ_GROUP Assignment
2.5. Design Guidelines x
2.5.1. Guidelines: Group Pin Placement 2.5.2. Reference Clock 2.5.3. Reset
2.6. Design Example x
2.6.1. Generate the Design Example
2.6.1. Generate the Design Example x
2.6.1.1. Design Example without Dynamic Reconfiguration 2.6.1.2. Dynamic Reconfiguration Design Examples
2.6.1.1. Design Example without Dynamic Reconfiguration x
2.6.1.1.1. Generate the Synthesis Design Example 2.6.1.1.2. Generate the Simulation Design Example
2.6.1.2. Dynamic Reconfiguration Design Examples x
2.6.1.2.1. Generate the Synthesis Design Example 2.6.1.2.2. Generate the Simulation Design Example
3. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP x
3.1. Release Information 3.2. Functional Description 3.3. Getting Started 3.4. I/O Standards 3.5. Design Guidelines 3.6. Design Example
3.2. Functional Description x
3.2.1. Top Level Interfaces 3.2.2. Clocks 3.2.3. Output Path 3.2.4. Input Path 3.2.5. Dynamic Reconfiguration
3.2.2. Clocks x
3.2.2.1. Clock Frequency Relationships
3.2.3. Output Path x
3.2.3.1. Output Path Data Alignment
3.2.4. Input Path x
3.2.4.1. Input Path Data Alignment
3.2.5. Dynamic Reconfiguration x
3.2.5.1. RTL Connectivity 3.2.5.2. Address Lookup 3.2.5.3. Reconfiguration Features and Register Addressing 3.2.5.4. Calibration Guidelines
3.2.5.1. RTL Connectivity x
3.2.5.1.1. Daisy Chain
3.2.5.2. Address Lookup x
3.2.5.2.1. Strobes 3.2.5.2.2. Parameter Table Example
3.2.5.3. Reconfiguration Features and Register Addressing x
3.2.5.3.1. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP Control Registers Addresses 3.2.5.3.2. Control Registers Description
3.2.5.4. Calibration Guidelines x
3.2.5.4.1. Strobe Enable Window Calibration 3.2.5.4.2. Output and Strobe Enable Minimum and Maximum Phase Settings
3.3. Getting Started x
3.3.1. Parameter Settings 3.3.2. Signals
3.3.1. Parameter Settings x
3.3.1.1. Read Latency 3.3.1.2. Write Latency
3.3.2. Signals x
3.3.2.1. Clock and Reset Interface Signals 3.3.2.2. Output Path Signals 3.3.2.3. Input Path Signals 3.3.2.4. Avalon Configuration Bus Interface Signals 3.3.2.5. Termination Signals
3.4. I/O Standards x
3.4.1. Input Buffer Reference Voltage (VREF) 3.4.2. On-Chip Termination (OCT)
3.4.1. Input Buffer Reference Voltage (VREF) x
3.4.1.1. Calibrated VREF Settings
3.4.2. On-Chip Termination (OCT) x
3.4.2.1. RZQ_GROUP Assignment 3.4.2.2. Manual Insertion of OCT Block
3.5. Design Guidelines x
3.5.1. Guidelines: Group Pin Placement 3.5.2. Reference Clock 3.5.3. Reset 3.5.4. Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank 3.5.5. Dynamic Reconfiguration 3.5.6. Timing
3.5.6. Timing x
3.5.6.1. Timing Components 3.5.6.2. Timing Constraints and Files 3.5.6.3. Timing Analysis 3.5.6.4. Timing Closure Guidelines
3.5.6.2. Timing Constraints and Files x
3.5.6.2.1. <variation_name>.sdc 3.5.6.2.2. <variation_name>_parameter.tcl 3.5.6.2.3. <variation_name>_ip_parameters.tcl 3.5.6.2.4. <variation_name>_pin_map.tcl 3.5.6.2.5. <variation_name>_report_timing.tcl 3.5.6.2.6. <variation_name>_report_timing_core.tcl
3.5.6.4. Timing Closure Guidelines x
3.5.6.4.1. Timing Closure: Dynamic Reconfiguration 3.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints 3.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints 3.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data 3.5.6.4.5. I/O Timing Violation 3.5.6.4.6. Internal FPGA Path Timing Violation
3.6. Design Example x
3.6.1. Generate the Design Example
3.6.1. Generate the Design Example x
3.6.1.1. Design Example without Dynamic Reconfiguration 3.6.1.2. Dynamic Reconfiguration Design Examples
3.6.1.1. Design Example without Dynamic Reconfiguration x
3.6.1.1.1. Generate the Hardware Design Example 3.6.1.1.2. Generate the Simulation Design Example
3.6.1.2. Dynamic Reconfiguration Design Examples x
3.6.1.2.1. Dynamic Reconfiguration Using Finite State Machine
4. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs x
4.1. Release Information 4.2. Functional Description 4.3. Getting Started 4.4. I/O Standards 4.5. Design Guidelines 4.6. Design Example 4.7. Application Specific Design Example
4.2. Functional Description x
4.2.1. Top Level Interfaces 4.2.2. Clocks 4.2.3. Output Path 4.2.4. Input Path 4.2.5. Dynamic Reconfiguration
4.2.2. Clocks x
4.2.2.1. Clock Frequency Relationships
4.2.3. Output Path x
4.2.3.1. Output Path Data Alignment
4.2.4. Input Path x
4.2.4.1. Input Path Data Alignment
4.2.5. Dynamic Reconfiguration x
4.2.5.1. RTL Connectivity 4.2.5.2. Address Lookup 4.2.5.3. Reconfiguration Features and Register Addressing 4.2.5.4. Calibration Guidelines
4.2.5.1. RTL Connectivity x
4.2.5.1.1. Daisy Chain
4.2.5.2. Address Lookup x
4.2.5.2.1. Strobes 4.2.5.2.2. Parameter Table Example
4.2.5.3. Reconfiguration Features and Register Addressing x
4.2.5.3.1. PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP and PHY Lite for Parallel Interfaces Intel Cyclone 10 GX IPs Address Registers 4.2.5.3.2. Control Registers Description
4.2.5.4. Calibration Guidelines x
4.2.5.4.1. Strobe Enable Window Calibration 4.2.5.4.2. Output and Strobe Enable Minimum and Maximum Phase Settings
4.3. Getting Started x
4.3.1. Parameter Settings 4.3.2. Signals
4.3.1. Parameter Settings x
4.3.1.1. Read Latency 4.3.1.2. Write Latency
4.3.2. Signals x
4.3.2.1. Clock and Reset Interface Signals 4.3.2.2. Output Path Signals 4.3.2.3. Input Path Signals 4.3.2.4. Avalon Configuration Bus Interface Signals 4.3.2.5. Termination Signals
4.4. I/O Standards x
4.4.1. Input Buffer Reference Voltage (VREF) 4.4.2. On-Chip Termination (OCT)
4.4.1. Input Buffer Reference Voltage (VREF) x
4.4.1.1. Calibrated VREF Settings
4.4.2. On-Chip Termination (OCT) x
4.4.2.1. RZQ_GROUP Assignment 4.4.2.2. Manual Insertion of OCT Block
4.5. Design Guidelines x
4.5.1. Guidelines: Group Pin Placement 4.5.2. Reference Clock 4.5.3. Reset 4.5.4. Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank 4.5.5. Dynamic Reconfiguration 4.5.6. Timing
4.5.6. Timing x
4.5.6.1. Timing Components 4.5.6.2. Timing Constraints and Files 4.5.6.3. Timing Analysis 4.5.6.4. Timing Closure Guidelines
4.5.6.2. Timing Constraints and Files x
4.5.6.2.1. <variation_name>.sdc 4.5.6.2.2. <variation_name>_parameter.tcl 4.5.6.2.3. <variation_name>_ip_parameters.tcl 4.5.6.2.4. <variation_name>_pin_map.tcl 4.5.6.2.5. <variation_name>_report_timing.tcl 4.5.6.2.6. <variation_name>_report_timing_core.tcl
4.5.6.4. Timing Closure Guidelines x
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration 4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints 4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints 4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data 4.5.6.4.5. I/O Timing Violation 4.5.6.4.6. Internal FPGA Path Timing Violation
4.6. Design Example x
4.6.1. Generate the Design Example
4.6.1. Generate the Design Example x
4.6.1.1. Design Example without Dynamic Reconfiguration 4.6.1.2. Dynamic Reconfiguration Design Examples
4.6.1.1. Design Example without Dynamic Reconfiguration x
4.6.1.1.1. Generate the Hardware Design Example 4.6.1.1.2. Generate the Simulation Design Example
4.6.1.2. Dynamic Reconfiguration Design Examples x
4.6.1.2.1. Dynamic Reconfiguration with Debug Kit Example of Accessing Dynamic Reconfiguration Control Registers using Avalon Controller 4.6.1.2.2. Dynamic Reconfiguration Using Finite State Machine
4.7. Application Specific Design Example x
4.7.1. Implementation using the PHY Lite for Parallel Interfaces IP
1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP
3. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP
4. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs
5. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
6. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide

This design example is a simulation design example that is capable to perform dynamic calibration for PHY Lite for Parallel Interfaces IP in Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.

The design example includes:
  • A fully configurable PHY Lite for Parallel Interfaces IP
  • An Avalon controller to perform address translation
  • A NIOS II processor to perform dynamic calibration for PHY Lite for Parallel Interfaces IP
  • A set of application program interface (API) to configure delay chains for PHY Lite for Parallel Interfaces IP
Figure 84. Dynamic Reconfiguration with Debug Kit Design Example
Table 90.  Dynamic Reconfiguration with Debug Kit Design Example Generated FilesThe example design folders are named differently in Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.
  • For Intel® Arria® 10, the example design folder is named as phylite_0_example design.
  • For Intel® Cyclone® 10 GX, the example design folder is named as phylite_c10gx_0_example_design.
Example Design Files Description
<example_design_folder>/readme.txt This file provide simple instructions to generate and use the example design.
<example_design_folder>/hello_world.c This is the main test program.
<example_design_folder>/phylite_debug_kit.qsys This is the system design file.
<example_design_folder>/phylite_dynamic_reconfigurations.c This file contains the set of APIs use in the test program.
<example_design_folder>/phylite_dynamic_reconfiguration.h This is the header file for the APIs.
<example_design_folder>/phylite_niosii_bridge.v <example_design_folder>/phylite_niosii_bridge_hw.tcl This is an interconnect module between PHY Lite for Parallel Interfaces IP and NIOS II processor.
<example_design_folder>/issp.tcl This is the In-System Source and Probes module. Use this file to reset the system and to probe the status of the interface_locked signal and dynamic calibration done status from NIOS II processor.
Table 91.  API Functions in Dynamic Reconfiguration Debug Kit Design Example
API Function Argument Return Value Description
hw_get_num_groups ID Integer Read from AVL_CTRL_REG_NUM_GROUPS register for the specified ID.
hw_get_group_info ID, GROUP_NUM {16'h0000, num_lanes[7:0], num_pins[7:0]} Read from AVL_CTRL_REG_GROUP_ INFO register for the specified ID and group number.

The return values are the number of lanes and number of pins available for the specified ID and group number.

hw_get_num_lanes ID, GROUP_NUM Integer Read from the AVL_CTRL_REG_GROUP_ INFO register for the specified ID and group number.

The return values are the number of lanes available for the specified ID and group number.

hw_get_num_pins ID, GROUP_NUM Integer Read from the AVL_CTRL_REG_GROUP_ INFO register for the specified ID and group number.

The return values are the number of pins available for the specified ID and group number.

hw_get_input_delay ID, GROUP_NUM, PIN_NUM, CSR Integer Read from the AVL_CTRL_REG_IDELAY register for the specified ID, group number, and pin ID.
Specified CSR to:
  • 0 to read from Avalon Controller register
  • 1 to read from CSR register
hw_get_output_delay ID, GROUP_NUM, PIN_NUM, CSR Integer Read from the AVL_CTRL_REG_ODELAY register for the specified ID, group number and pin number.
Specified CSR to:
  • 0 to read from Avalon Controller register
  • 1 to read from CSR register
hw_get_strobe_input_delay ID, GROUP_NUM, PIN_NUM, CSR Integer Read from the AVL_CTRL_REG_DQS_DELAY delay register for the specified ID, group number and pin number.
Specified CSR to:
  • 0 to read from Avalon Controller register
  • 1 to read from CSR register
hw_get_strobe_enable_delay ID, GROUP_NUM, PIN_NUM, CSR Integer Read from the AVL_CTRL_REG_DQS_EN_DELAY register for the specified ID, group number and pin number.
Specified CSR to:
  • 0 to read from Avalon Controller register
  • 1 to read from CSR register
hw_get_strobe_enable_phase ID, GROUP_NUM, PIN_NUM, CSR Integer Read from the AVL_CTRL_REG_DQS_EN_PHASE_SHIFT register for the specified ID, group number and pin number.
Specified CSR to:
  • 0 to read from Avalon Controller register
  • 1 to read from CSR register
hw_get_read_valid_enable_delay ID, GROUP_NUM, PIN_NUM, CSR Integer Read from the AVL_CTRL_REG_RD_VALID_DELAY register for the specified ID, group number and pin number.
Specified CSR to:
  • 0 to read from Avalon Controller register
  • 1 to read from CSR register
hw_set_input_delay ID, GROUP_NUM, PIN_NUM, input delay value (integer) — Write to AVL_CTRL_REG_IDELAY register for the specified ID, group number and pin number.

Refer to the Control Registers Description topic for valid value range.

hw_set_output_delay ID, GROUP_NUM, PIN_NUM, output delay value (integer) — Write to AVL_CTRL_REG_ODELAY register for the specified ID, group number and pin number.

Refer to the Control Registers Description topic for valid value range.

hw_set_strobe_input_delay ID, GROUP_NUM, PIN_NUM, strobe input delay value (integer) — Write to AVL_CTRL_REG_DQS_DELAY register for the specified ID, group number and pin number.

Refer to the Control Registers Description topic for valid value range.

hw_set_strobe_enable_delay ID, GROUP_NUM, PIN_NUM, strobe enable delay value (integer) — Write to AVL_CTRL_REG_DQS_EN_DELAY register for the specified ID, group number and pin number.

Refer to the Control Registers Description topic for valid value range.

hw_set_strobe_enable_phase ID, GROUP_NUM, PIN_NUM, strobe enable phase value (integer) — Write to AVL_CTRL_REG_DQS_EN_PHASE_SHIFT register for the specified ID, group number and pin number.

Refer to the Control Registers Description topic for valid value range.

hw_set_read_valid_enable_delay ID, GROUP_NUM, PIN_NUM, read valid enable delay value (integer) — Write to AVL_CTRL_REG_RD_VALID_DELAY register for the specified ID, group number and pin number.

Refer to the Control Registers Description topic for valid value range.

Related Information

Avalon Controller

The example design provides an Avalon controller to simplify the access to the dynamic reconfiguration registers of an interface. The Avalon controller is useful when there are multiple groups or instantiation of the PHY Lite for Parallel Interfaces IP. A single controller can support multiple interfaces in an I/O column.

Figure 85. Avalon Controller


The input interface is as follows:

avl_in_address[31:0] = {8'h00,interface_id[3:0],grp[4:0],pin[5:0],csr[0],register[7:0]}

Note: There is no look-up stage here. The Avalon controller automatically looks up and caches all the necessary data.
Table 92.  Avalon Controller RegistersThis table lists the available registers in the Avalon controller. For more information, refer to the Control Registers Description topic.
Register [7:0] Register Name Pin [5:0] Csr[0] Register Access Type Data on avl_readdata / writedata Description
8'h00 AVL_CTRL_REG_NUM_GROUPS 0 0: Access to Avalon register.

Avalon register: RO

CSR register: N/A

 {24'h000000,num_grps[7:0]} Number of groups within an interface.
8'h01 AVL_CTRL_REG_GROUP_INFO 0 0: Access to Avalon register.

Avalon register: RO

CSR register: N/A

 {16'h0000,num_lanes[7:0],num_pins[7:0]} Number of pins within a group.
8'h02 AVL_CTRL_REG_IDELAY 0-47 0: Access to Avalon register.

Avalon register: RW

CSR register: N/A

 {23'h000000,dq_delay[8:0]} Pin input delay. Use this register to set pin PVT compensated input delay.
8'h03 AVL_CTRL_REG_ODELAY 0-47

0: Access to Avalon register.

1: Access to CSR register. Only read operation is allowed.

Avalon register: RW

CSR register: RO

 {19'h00000,output_delay[12:0]} Pin output delay. Use this register to read and set the pin output delay.
8'h04 AVL_CTRL_REG_DQS_DELAY 0: DQS A

1: DQS B

18 		0: Access to Avalon register.

Avalon register: RW

CSR register: N/A

 {22'h000000,dqs_delay[9:0]} Strobe input delay of a pin. Use this register to set the strobe PVT compensated input delay.
8'h05 AVL_CTRL_REG_DQS_EN_DELAY 0

0: Access to Avalon register.

1: Access to CSR register. Only read operation is allowed.

Avalon register: RW

CSR register: RO

 {26'h0000000,dqs_en_delay[5:0]} Strobe enable input delay of a pin. Use this register to set the strobe enable delay.
8'h06 AVL_CTRL_REG_DQS_EN_PHASE_SHIFT 0: DQS A

1: DQS B

18

0: Access to Avalon register.

1: Access to CSR register. Only read operation is allowed.

Avalon register: RW

CSR register: RO

 {19'h00000,phase[12:0]} Strobe enable input phase of a pin. Use this register to set the strobe enable phase.
8'h07 AVL_CTRL_REG_RD_VALID_DELAY 0

0: Access to Avalon register.

1: Access to CSR register. Only read operation is allowed.

Avalon register: RW

CSR register: RO

 {25'h0000000,rd_vld_delay[6:0]} Read val to set the read valid delay.
Note: The example Avalon controller does not currently support VREF reconfiguration.
Related Information

Example of Accessing Dynamic Reconfiguration Control Registers using Avalon Controller

This example shows the steps to access the dynamic reconfiguration control registers using Avalon controller with the following PHY Lite for Parallel Interfaces IP settings:
  • Number of groups: 1. The group index is automatically set to 0x00.
  • Interface ID: 0x04
  • Pin width: 5
  • Strobe configuration: Differential
Below is the Avalon address value to read AVL_CTRL_REG_DQS_DELAY Avalon register (strobe pin delay) at offset 0x04:
Note: The PHY Lite for Parallel Interfaces IP fixes the strobe pin as pin[0]. 
avl_in_address[31:0] = {8'h00,interface_id[3:0],grp[4:0],pin[5:0],csr[0],register[7:0]} 
avl_in_address[31:0] = {8'h00,0x04,0x00,0x00,0x00,0x04}
Below is the Avalon address value to read AVL_CTRL_REG_IDELAY Avalon register (input data pin) at offset 0x02 for data pin 4. The pin number for data pin 4 is 0x06: 
avl_in_address[31:0] = {8'h00,interface_id[3:0],grp[4:0],pin[5:0],csr[0],register[7:0]} 
avl_in_address[31:0] = {8'h00,0x04,0x00,0x06,0x00,0x02}

Generate the Dynamic Reconfiguration with Debug Kit Design Example

  1. In Intel® Quartus® Prime, select File > New Project Wizard to create a new project directory and specify phylite_debug_kit as the project name.
  2. Select device and instantiate PHY Lite for Parallel Interfaces IP and turn on the Use dynamic reconfiguration option.
  3. Click Generate Example Design.
  4. In your example design directory, open the phylite_debug_kit.qsys file and click Generate HDL to generate the .qsys design example files.
  5. In Intel® Quartus® Prime, right click on the design example project and select Settings.
  6. In Files tab, browse to the <generated design example folder/phylite_debug_kit> and add in phylite_debug_kit.qip file into your project.
  7. Select Start Compilation to compile the design example project.
  8. In Intel® Quartus® Prime, select Tools > Nios II Software Build Tool for Eclipse. Create a new workspace when prompted.
  9. In Nios II - Eclipse software, select File > New > Nios II Application and BSP from Template.
  10. In the Nios II Application and BSP from Template window, select phylite_debug_kit_sopcinfo file in SOPC Information File name parameter to load the CPU settings.
  11. Specify a project name in the Project name parameter.
  12. Select Hello World for the Project Template.
  13. Click Finish to generate the project.
  14. Copy hello_world.c, phylite_dynamic_reconfiguration.c, and phylite_dynamic_reconfiguration.h files from the generated example design folder into your Eclipse project folder. You can refresh the Nios II Eclipse window by pressing F5 to make sure these files are added into your Eclipse project.
  15. In the Nios II Eclipse window, click Project > Build Project to generate .elf file.
  16. Run the following command in Nios II Command Shell to convert the .elf file into .hex. 
    elf2hex --input=<elf_filename>.elf --base=0x40000 --end=0x7ffff --width=32 --output=phylite_debug_kit_inst_mem.hex
  17. Copy and add the phylite_debug_kit_inst_mem.hex file into the ed_synth project folder.
  18. Add the following command in the ed_synth.qsf to include the phylite_debug_kit_inst_mem.hex in your project compilation.
    set_global_assignment -name MISC_FILE phylite_debug_kit_inst_mem.hex
  19. Compile the ed_synth project file to generate .sof file to run the example design on your hardware.

Run the Dynamic Reconfiguration with Debug Kit Design Example

  1. Download the phylite_debug_kit.sof file into the FPGA.
  2. From the Quartus installation directory, double click on the Nios II Command Shell.bat to launch the Intel Nios® II command shell (command shell A). Repeat the same step to launch a second command shell (command shell B).
  3. In command shell B, use the following command to run Nios II terminal application for result printouts.
    nios2-terminal --cable=<jtag_cable_num>
  4. Use the following command in command shell A to reset the system and start the dynamic reconfiguration application.
    quartus_stp -t issp.tcl phylite_debug_kit.qpf
18 Strobe logic B is only used by the negative pin of complementary strobes
Level Two Title