Visible to Intel only — GUID: ayi1599793523510
Ixiasoft
Visible to Intel only — GUID: ayi1599793523510
Ixiasoft
3.3.2.2. Output Path Signals
Signal Name | Direction | Width | Description |
---|---|---|---|
group_<n>_oe_from_core | Input | Quarter-rate: 4 x PIN_WIDTH Half-rate: 2 x PIN_WIDTH Full-rate: 1 x PIN_WIDTH |
Output enable signal from core logic. Synchronous to the core_clk_out output from the IP. |
group_<n>_data_from_core | Input | Quarter rate-DDR: 8 x PIN_WIDTH Half-rate DDR: 4 x PIN_WIDTH Full-rate DDR: 2 x PIN_WIDTH Quarter-rate SDR: 4 x PIN_WIDTH Half-rate SDR: 2 x PIN_WIDTH Full-rate SDR: 1 x PIN_WIDTH |
Data signal from core logic. Synchronous to the core_clk_out output from the IP. |
group_<n>_strobe_out_in | Input | Quarter-rate: 8 Half-rate: 4 Full-rate: 2 |
Strobe signal from core logic. Synchronous to the core_clk_out output from the IP.
Note: This path is always DDR.
|
group_<n>_strobe_out_en | Input | Quarter-rate: 4 Half-rate: 2 Full-rate: 1 |
Strobe output enable from core logic. Synchronous to the core_clk_out output from the IP. |
group_<n>_data_out/group_<n>_data_io | Output/Bidirectional | 1 to 48 if data configuration is Single Ended | Data output from PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP. Synchronous to the group_<n>_strobe_out or group_<n>_strobe_io output from the IP. If the Pin Type parameter is set to Output, the group_<n>_data_out signals are used. If the Pin Type parameter is set to Bidirectional, the group_<n>_data_io signals are used.
Note: PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP does not support differential data pins.
|
group_<n>_strobe_out /group_<n>_strobe_io | Output/Bidirectional | 1 | Positive output strobe fromPHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP. If the Pin Type is set to Output, the group_<n>_strobe_out signal is used. If the Pin Type is set to Bidirectional the group_<n>_strobe_io signal is used. The Use Separate Strobes parameter forces the use of the group_<n>_strobe_out signal with a Bidirectional Pin Type. |
group_<n>_strobe_out_n /group_<n>_strobe_io_n | Output/Bidirectional | 1 | Negative output strobe from PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP. This is used if the Strobe Configuration is set to Differential or Complementary. If the Pin Type is set to Output, the group_<n>_strobe_out_n signal is used. If the Pin Type is set to Bidirectional, the group_<n>_strobe_io_n signal is used. The Use Separate Strobes parameter forces the use of the group_<n>_strobe_out_n signal with a Bidirectional Pin Type. |