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1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP
3. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP
4. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs
5. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
6. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide
3.5.6.4.1. Timing Closure: Dynamic Reconfiguration
3.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
3.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
3.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
3.5.6.4.5. I/O Timing Violation
3.5.6.4.6. Internal FPGA Path Timing Violation
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration
4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
4.5.6.4.5. I/O Timing Violation
4.5.6.4.6. Internal FPGA Path Timing Violation
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3.6.1. Generate the Design Example
You can generate a design example by clicking Generating Example Design in the IP Parameter Editor.
The software generates a user defined directory in which the design example files reside.
There are two variants of design example available for PHY Lite for Parallel Interfaces IP:
- Variant without dynamic reconfiguration design example
- Variant with dynamic reconfiguration design example
Design Example Variant | Design Files | Description | |
---|---|---|---|
Dynamic Reconfiguration | OFF | ed_synth.qsys (synthesis only) | Consists of configurablePHY Lite for Parallel Interfaces IP instance. |
ed_sim.qsys (simulation only) | Consists of sim_ctrl, agent, addr/cmd and PHY Lite for Parallel Interfaces IP instances. Perform read and write transaction verification. |
||
ON | ed_sim.qsys (simulation only) | Consists of sim_ctrl, agent, addr/cmd, cfg_ctrl, avl_ctrl and PHY Lite for Parallel Interfaces IP instances. This design example demonstrates dynamic reconfiguration and uses FSM to perform calibration. |