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1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP
3. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP
4. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs
5. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
6. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide
3.5.6.4.1. Timing Closure: Dynamic Reconfiguration
3.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
3.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
3.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
3.5.6.4.5. I/O Timing Violation
3.5.6.4.6. Internal FPGA Path Timing Violation
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration
4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
4.5.6.4.5. I/O Timing Violation
4.5.6.4.6. Internal FPGA Path Timing Violation
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3.4.2.2. Manual Insertion of OCT Block
You may also instantiate the OCT Intel FPGA IP separately in your project and connect the termination ports to the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP.
- Expose the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP termination ports by disable Use Default OCT Values.
- Select the available OCT values in the Input OCT Value parameter. This displays the Expose termination ports parameter.
Note: For supported input and output OCT values, refer to the I/O Standards topic.
- Select Expose termination ports to expose the termination ports in the IP.
- Connect the termination ports to a OCT Intel FPGA IP either in power-up or user mode.
Figure 45. RTL View of PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP Interfacing with OCT Intel FPGA IP in User Mode
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