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1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP
3. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP
4. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs
5. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
6. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide
3.5.6.4.1. Timing Closure: Dynamic Reconfiguration
3.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
3.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
3.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
3.5.6.4.5. I/O Timing Violation
3.5.6.4.6. Internal FPGA Path Timing Violation
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration
4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
4.5.6.4.5. I/O Timing Violation
4.5.6.4.6. Internal FPGA Path Timing Violation
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2.2.3.1.1. Clock Frequency Relationships
The following equations describe the relationships between the clock domains available in the PHY Lite for Parallel Interfaces IP.
Core Clock Rate = Interface clock frequency / Core clock frequency
VCO frequency Multiplier Factor = VCO clock frequency 3 / Interface clock frequency
3 You can obtain this value from the VCO clock frequency parameter under General Tab in the IP parameter editor.