Visible to Intel only — GUID: bhc1410941855459
Ixiasoft
1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP
3. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP
4. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs
5. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
6. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide
3.5.6.4.1. Timing Closure: Dynamic Reconfiguration
3.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
3.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
3.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
3.5.6.4.5. I/O Timing Violation
3.5.6.4.6. Internal FPGA Path Timing Violation
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration
4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
4.5.6.4.5. I/O Timing Violation
4.5.6.4.6. Internal FPGA Path Timing Violation
Visible to Intel only — GUID: bhc1410941855459
Ixiasoft
1.2. Features
The PHY Lite for Parallel Interfaces IP:
- Supports input, output, and bidirectional data channels.
- Supports DQS-group based data capture, with up to 48 I/Os (including data, strobes, PLL reference clock) per IP for Intel® Agilex™ devices and 48 I/Os (including strobes) per group for Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices.
- Supports DQS gating/ungating circuitry for strobe-based interfaces.
- Supports output delays via interpolator.
- Supports dynamic on-chip termination (OCT) control.
- Supports quarter-rate for Intel® Agilex™ devices and quarter-rate to half-rate and half-rate to full-rate of the interface clock conversions for Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices.
- Supports input, output, and read/DQS/OCT enable paths.
- Supports single data rate (SDR) and double data rate (DDR) at the I/Os.
- Supports PHY clock tree.
- Supports dynamically reconfigurable delay chains using Avalon® memory-mapped interface for Intel® Agilex™ , Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices.
- Supports process, voltage, and temperature (PVT) or non-PVT compensated input and DQS delay chains
Note: The non-PVT compensated component of the input delay is set through the .qsf assignment in the Intel® Quartus® Prime software.