Visible to Intel only — GUID: wtj1599629827202
Ixiasoft
Visible to Intel only — GUID: wtj1599629827202
Ixiasoft
2.2.3.2.1. Output Path Data Alignment
The group_data_from_core and group_oe_from_core signals are arranged in time slices, which are separated into the individual pins in the group. The first time slice is on the LSBs of the buses, which matches the Intel FPGA PHY interface (AFI) bus ordering of the External Memory Interfaces IP.
Example of time slices with individual pins correlation:
{time(n),time(n-1),time(n-2),... time(0)}
Where time0 = {pin(n),pin(n-1),pin(n-2),...pin0}
The following figure shows how data from group_<X>_data_from_core are written on the group_<X>_data_io relative to group_<X>_strobe_io.
Note that group_<X>_strobe_io is in tristate outside data valid window.