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1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP
3. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP
4. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs
5. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
6. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide
3.5.6.4.1. Timing Closure: Dynamic Reconfiguration
3.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
3.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
3.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
3.5.6.4.5. I/O Timing Violation
3.5.6.4.6. Internal FPGA Path Timing Violation
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration
4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
4.5.6.4.5. I/O Timing Violation
4.5.6.4.6. Internal FPGA Path Timing Violation
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3.5.6.4.6. Internal FPGA Path Timing Violation
If timing violations are reported at the internal FPGA paths (such as <instance_name>_usr_clk or <instance_name>_phy_clk_*), consider the following guidelines:
If setup time violation is reported, lower the clock rate of the user logic from full-rate to half-rate, or from half-rate to quarter-rate. This reduces the frequency requirement of the IP core-to-core data transfer.
If hold time violation is observed, you may increase hold uncertainty value to equal or higher than the violation amount in the .sdc file. This will provide a more stringent constraint during design fitting. Following is an example to increase the hold uncertainty.
If {$::quartus(nameofexecutable) != “quartus_sta”}{
set_clock_uncertainty -from [<instance_name>_phy_clk_*] -to [<instance_name>_phy_clk_*] -hold 0.3 -add
set_clock_uncertainty -from [<instance_name>_usr_clk] -to [<instance_name>_usr_clk] -hold 0.3 -add
}
However, increasing the hold uncertainty value may cause setup timing violation at slow corner.