Visible to Intel only — GUID: bhc1410941943098
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1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP
3. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP
4. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs
5. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
6. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide
3.5.6.4.1. Timing Closure: Dynamic Reconfiguration
3.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
3.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
3.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
3.5.6.4.5. I/O Timing Violation
3.5.6.4.6. Internal FPGA Path Timing Violation
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration
4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
4.5.6.4.5. I/O Timing Violation
4.5.6.4.6. Internal FPGA Path Timing Violation
Visible to Intel only — GUID: bhc1410941943098
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4.4. I/O Standards
The PHY Lite for Parallel Interfaces IP allows you to set I/O standards on the pins associated with the generated configuration. The I/O standard controls the available strobe configurations and OCT settings for all groups.
I/O Standard | Valid Input Terminations (Ω) 11 | Valid Output Calibrated/Uncalibrated Terminations (Ω)11 | RZQ (Ω) 12 | Differential/Complementary I/O Support |
---|---|---|---|---|
SSTL-12 13 | 60, 120 | 40, 60 | 240 | Yes |
SSTL-125 13 | 60, 120 | 34, 40 | 240 | Yes |
SSTL-135 13 | 60, 120 | 34, 40 | 240 | Yes |
SSTL-15 13 | 60, 120 | 34, 40 | 240 | Yes |
SSTL-15 Class I 14 | 0, 50 | 0, 50 | 100 | Yes |
SSTL-15 Class II14 | 0, 50 | 0, 25 | 100 | Yes |
SSTL-18 Class I14 | 0, 50 | 0, 50 | 100 | Yes |
SSTL-18 Class II14 | 0, 50 | 0, 25 | 100 | Yes |
1.2-V HSTL Class I14 | 0, 50 | 0, 50 | 100 | Yes |
1.2-V HSTL Class II14 | 0, 50 | 0, 25 | 100 | Yes |
1.5-V HSTL Class I14 | 0, 50 | 0, 50 | 100 | Yes |
1.5-V HSTL Class II14 | 0, 50 | 0, 25 | 100 | Yes |
1.8-V HSTL Class I14 | 0, 50 | 0, 50 | 100 | Yes |
1.8-V HSTL Class II14 | 0, 50 | 0, 25 | 100 | Yes |
1.2-V POD | 34, 40, 48, 60, 80, 120, 240 | 34, 40, 48, 60 | 240 | Yes |
1.2-V | — | — | — | No |
1.5-V | — | — | — | No |
1.8-V | — | — | — | No |
I/O Standard | Valid Input Terminations (Ω) 11 | Valid Output Calibrated/Uncalibrated Terminations (Ω)11 | RZQ (Ω) 12 | Differential/Complementary I/O Support |
---|---|---|---|---|
SSTL-12 15 | 60, 120 | 40, 60 | 240 | Yes |
SSTL-125 15 | 60, 120 | 34, 40 | 240 | Yes |
SSTL-135 15 | 60, 120 | 34, 40 | 240 | Yes |
SSTL-15 15 | 60, 120 | 34, 40 | 240 | Yes |
SSTL-15 Class I 16 | 0, 50 | 0, 50 | 100 | Yes |
SSTL-15 Class II16 | 0, 50 | 0, 25 | 100 | Yes |
SSTL-18 Class I16 | 0, 50 | 0, 50 | 100 | Yes |
SSTL-18 Class II16 | 0, 50 | 0, 25 | 100 | Yes |
1.2-V HSTL Class I16 | 0, 50 | 0, 50 | 100 | Yes |
1.2-V HSTL Class II16 | 0, 50 | 0, 25 | 100 | Yes |
1.5-V HSTL Class I16 | 0, 50 | 0, 50 | 100 | Yes |
1.5-V HSTL Class II16 | 0, 50 | 0, 25 | 100 | Yes |
1.8-V HSTL Class I16 | 0, 50 | 0, 50 | 100 | Yes |
1.8-V HSTL Class II16 | 0, 50 | 0, 25 | 100 | Yes |
1.2-V POD | 34, 40, 48, 60, 80, 120, 240 | 34, 40, 48, 60 | 240 | Yes |
1.2-V | — | — | — | No |
1.5-V | — | — | — | No |
1.8-V | — | — | — | No |
11 0 is equivalent to no termination.
12 RZQ pin is not required for uncalibrated output terminations.
13 Use this I/O standard if input termination is required with interface frequency more than 533 MHz.
14 Use this I/O standard if input termination is required with interface frequency equal or less than 533 MHz.
15 Use this I/O standard if input termination is required with interface frequency more than 533 MHz.
16 Use this I/O standard if input termination is required with interface frequency equal or less than 533 MHz.