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1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP
3. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP
4. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs
5. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
6. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide
3.5.6.4.1. Timing Closure: Dynamic Reconfiguration
3.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
3.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
3.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
3.5.6.4.5. I/O Timing Violation
3.5.6.4.6. Internal FPGA Path Timing Violation
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration
4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
4.5.6.4.5. I/O Timing Violation
4.5.6.4.6. Internal FPGA Path Timing Violation
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2.2.3.1. Clocks
The PHY Lite for Parallel Interfaces IP uses a reference clock that is sourced from a dedicated clock pin to the PLL inside the IP. This PLL provides four clock domains for the output and input paths.
Clock Domain | Description |
---|---|
Core clock | This clock is generated internally by the IP and it is used for all transfers between the FPGA core fabric and I/O banks. The clock phase alignment circuitry ensures that this clock is kept in phase with the PHY clock for core-to-periphery and periphery-to-core transfers. |
PHY clock | This clock is used internally by the IP for PHY circuitry running at the same frequency as the core clock. |
VCO clock | This clock is generated internally by the PLL. It is used by both the input and output paths to generate PVT compensated delays in the interpolator. |
Interface clock | This is the clock frequency of the external device connected to the FPGA I/Os. |
Core Clock Rate | Speed Grade –1 (MHz) | Speed Grade –2 (MHz) | Speed Grade –3 (MHz) | |||
---|---|---|---|---|---|---|
Min | Max | Min | Max | Min | Max | |
Quarter | 100 | 1,200 | 100 | 933 | 100 | 933 |
Note: The PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP supports only quarter core clock rate.