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1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP
3. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP
4. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs
5. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
6. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide
3.5.6.4.1. Timing Closure: Dynamic Reconfiguration
3.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
3.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
3.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
3.5.6.4.5. I/O Timing Violation
3.5.6.4.6. Internal FPGA Path Timing Violation
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration
4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
4.5.6.4.5. I/O Timing Violation
4.5.6.4.6. Internal FPGA Path Timing Violation
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2.2.4.3.2. Output and Strobe Enable Minimum and Maximum Phase Settings
When dynamically reconfiguring the interpolator phase settings, keep the values within the ranges in the following table to ensure proper operation of the circuitry.
VCO Multiplication Factor | Core Rate | Minimum Interpolator Phase | Maximum Interpolator Phase | ||
---|---|---|---|---|---|
Output | Bidirectional | Bidirectional with OCT Enabled | |||
1 | Full | 0x080 | 0x100 | 0x100 | 0xA80 |
Half | 0x080 | 0x100 | 0x100 | 0xBC0 | |
Quarter | 0x080 | 0x100 | 0x100 | 0xA00 | |
2 | Full | 0x080 | 0x100 | 0x180 | 0x1400 |
Half | 0x080 | 0x100 | 0x180 | 0x1400 | |
Quarter | 0x080 | 0x100 | 0x180 | 0x1400 | |
4 | Full | 0x080 | 0x100 | 0x280 | 0x1FFF |
Half | 0x080 | 0x100 | 0x280 | 0x1FFF | |
Quarter | 0x080 | 0x100 | 0x280 | 0x1FFF | |
8 | Full | 0x080 | 0x100 | 0x480 | 0x1FFF |
Half | 0x080 | 0x100 | 0x480 | 0x1FFF | |
Quarter | 0x080 | 0x100 | 0x480 | 0x1FFF |