Visible to Intel only — GUID: rsa1601257547629
Ixiasoft
1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP
3. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP
4. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs
5. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
6. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide
3.5.6.4.1. Timing Closure: Dynamic Reconfiguration
3.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
3.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
3.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
3.5.6.4.5. I/O Timing Violation
3.5.6.4.6. Internal FPGA Path Timing Violation
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration
4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
4.5.6.4.5. I/O Timing Violation
4.5.6.4.6. Internal FPGA Path Timing Violation
Visible to Intel only — GUID: rsa1601257547629
Ixiasoft
2.2.2. Intel® Agilex™ Input DQS/Strobe Tree
The input DQS/strobe tree is a balanced clock network that distributes the read capture strobe (such as DQS/DQS#) from the external device to the read capture registers inside the I/Os.
The DQS/strobe tree is used for input and bidirectional pin types.
Within every bank, only certain physical pins at specific locations can drive the input DQS/strobe trees. The pin locations that can drive the input DQS/strobe trees vary, depending on the size of the group.
Bank Lane used by Data Pins | Group Size | Strobe Pins 1 2 |
---|---|---|
0 | x8 / x9 | Pin 4, 5 |
1 | x8 / x9 | Pin 16, 17 |
2 | x8 / x9 | Pin 28, 29 |
3 | x8 / x9 | Pin 40, 41 |
0, 1 | x18 | Pin 4, 5 |
2, 3 | x18 | Pin 28, 29 |
1, 2 | x36 | Pin 16, 17 |
0, 1, 2 | x36 | Pin 16, 17 |
1, 2, 3 | x36 | Pin 16, 17 |
0, 1, 2, 3 | x36 | Pin 16, 17 |
1 For strobe pin, use either pin for single-ended and use both pins for differential.
2 In quarter rate, unused strobe pin cannot be used as data pins.