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Ixiasoft
1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. Golden System Reference Design and Design Examples
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Stratix® 10 SoC FPGA Boot Flow
8. Stratix® 10 SoC FPGA Boot User Guide Archives
9. Document Revision History for Stratix® 10 SoC FPGA Boot User Guide
4.1. Overview
4.2. Quartus® Prime Hardware Project Compilation
4.3. Bootloader Software Compilation
4.4. Programming File Generator
4.5. Configuration over JTAG
4.6. Configuration from QSPI
4.7. Configuration over AVST
4.8. Configuration via Protocol
4.9. Remote System Update
4.10. Partial Reconfiguration
Visible to Intel only — GUID: vwb1502123013869
Ixiasoft
1. Introduction
Updated for: |
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Intel® Quartus® Prime Design Suite 22.4 |
This user guide describes the Stratix® 10 SoC FPGA boot flow, boot sources, and how to generate a bitstream required for successful booting of the device. The details provided in this boot user guide include:
- The typical boot flows and boot stages of the Stratix® 10 SoC FPGA.
- The supported system layout for different hard processor system (HPS) boot modes.
- How to use Quartus® Prime Pro Edition to generate the configuration bitstream.