L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

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ID 683111
Date 10/27/2023
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Quick Start Guide 3. Interface Overview 4. Parameters 5. Designing with the IP Core 6. Block Descriptions 7. Interrupts 8. Registers 9. Testbench and Design Example 10. Troubleshooting and Observing the Link A. PCI Express Core Architecture B. TX Credit Adjustment Sample Code C. Root Port Enumeration D. Document Revision History
1. Introduction x
1.1. Avalon-ST Interface with Optional SR-IOV for PCIe Introduction 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Recommended Fabric Speed Grades 1.6. Performance and Resource Utilization 1.7. Transceiver Tiles 1.8. PCI Express IP Core Package Layout 1.9. Channel Availability
2. Quick Start Guide x
2.1. Design Components 2.2. Hardware and Software Requirements 2.3. Directory Structure 2.4. Generating the Design Example 2.5. Simulating the Design Example 2.6. Compiling the Design Example and Programming the Device 2.7. Installing the Linux Kernel Driver 2.8. Running the Design Example Application
3. Interface Overview x
3.1. Avalon-ST RX Interface 3.2. Avalon-ST TX Interface 3.3. TX Credit Interface 3.4. TX and RX Serial Data 3.5. Clocks 3.6. Function-Level Reset (FLR) Interface 3.7. Control Shadow Interface for SR-IOV 3.8. Configuration Extension Bus Interface 3.9. Hard IP Reconfiguration Interface 3.10. Interrupt Interfaces 3.11. Power Management Interface 3.12. Reset 3.13. Transaction Layer Configuration Interface 3.14. PLL Reconfiguration Interface 3.15. PIPE Interface (Simulation Only)
4. Parameters x
4.1. Stratix 10 Avalon-ST Settings 4.2. Multifunction and SR-IOV System Settings 4.3. Base Address Registers 4.4. Device Identification Registers 4.5. TPH/ATS Capabilities 4.6. PCI Express and PCI Capabilities Parameters 4.7. Configuration, Debug and Extension Options 4.8. PHY Characteristics 4.9. Example Designs
4.6. PCI Express and PCI Capabilities Parameters x
4.6.1. Device Capabilities 4.6.2. Link Capabilities 4.6.3. MSI and MSI-X Capabilities 4.6.4. Slot Capabilities 4.6.5. Power Management 4.6.6. Vendor Specific Extended Capability (VSEC)
5. Designing with the IP Core x
5.1. Generation 5.2. Simulation 5.3. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 5.4. Integration and Implementation 5.5. Required Supporting IP Cores 5.6. Channel Layout and PLL Usage
5.2. Simulation x
5.2.1. Selecting Serial or PIPE Simulation
5.4. Integration and Implementation x
5.4.1. Clock Requirements 5.4.2. Reset Requirements
5.5. Required Supporting IP Cores x
5.5.1. Hard Reset Controller 5.5.2. TX PLL
6. Block Descriptions x
6.1. Interfaces 6.2. Errors reported by the Application Layer 6.3. Power Management 6.4. Transaction Ordering 6.5. RX Buffer
6.1. Interfaces x
6.1.1. TLP Header and Data Alignment for the Avalon-ST RX and TX Interfaces 6.1.2. Avalon-ST 256-Bit RX Interface 6.1.3. Avalon-ST 512-Bit RX Interface 6.1.4. Avalon-ST 256-Bit TX Interface 6.1.5. Avalon-ST 512-Bit TX Interface 6.1.6. TX Credit Interface 6.1.7. Interpreting the TX Credit Interface 6.1.8. Clocks 6.1.9. Update Flow Control Timer and Credit Release 6.1.10. Function-Level Reset (FLR) Interface 6.1.11. Resets 6.1.12. Interrupts 6.1.13. Control Shadow Interface for SR-IOV 6.1.14. Transaction Layer Configuration Space Interface 6.1.15. Configuration Extension Bus Interface 6.1.16. Hard IP Status Interface 6.1.17. Hard IP Reconfiguration 6.1.18. Power Management Interface 6.1.19. Serial Data Interface 6.1.20. PIPE Interface 6.1.21. Test Interface 6.1.22. PLL IP Reconfiguration 6.1.23. Message Handling
6.1.2. Avalon-ST 256-Bit RX Interface x
6.1.2.1. Avalon-ST RX Interface Three- and Four-Dword TLPs 6.1.2.2. Avalon-ST RX Interface rx_st_ready Deasserts for the 256-Bit Interface 6.1.2.3. Avalon-ST RX Interface rx_st_valid Deasserts 6.1.2.4. Avalon-ST RX Back-to-Back Transmission 6.1.2.5. Avalon-ST RX Interface Single-Cycle TLPs
6.1.3. Avalon-ST 512-Bit RX Interface x
6.1.3.1. PCIe TLP Layout Using the 512-Bit Interface
6.1.4. Avalon-ST 256-Bit TX Interface x
6.1.4.1. Avalon-ST TX Three- and Four-Dword TLPs 6.1.4.2. Avalon-ST TX Interface tx_st_ready Deassertion 6.1.4.3. Assertion and Deassertion of Avalon-ST TX Interface tx_st_valid
6.1.12. Interrupts x
6.1.12.1. MSI and Legacy Interrupts
6.1.23. Message Handling x
6.1.23.1. Endpoint Received Messages 6.1.23.2. Endpoint Transmitted Messages
6.2. Errors reported by the Application Layer x
6.2.1. Error Handling
6.3. Power Management x
6.3.1. Endpoint D3 Entry 6.3.2. End Point D3 Exit 6.3.3. Exit from D3 hot 6.3.4. Exit from D3 cold 6.3.5. Active State Power Management
6.4. Transaction Ordering x
6.4.1. TX TLP Ordering 6.4.2. RX TLP Ordering
6.5. RX Buffer x
6.5.1. Retry Buffer 6.5.2. Configuration Retry Status
7. Interrupts x
7.1. Interrupts for Endpoints
7.1. Interrupts for Endpoints x
7.1.1. MSI and Legacy Interrupts 7.1.2. MSI-X 7.1.3. Implementing MSI-X Interrupts 7.1.4. Legacy Interrupts
8. Registers x
8.1. Configuration Space Registers
8.1. Configuration Space Registers x
8.1.1. Register Access Definitions 8.1.2. PCI Configuration Header Registers 8.1.3. PCI Express Capability Structures 8.1.4. Intel Defined VSEC Capability Header 8.1.5. General Purpose Control and Status Register 8.1.6. Uncorrectable Internal Error Status Register 8.1.7. Uncorrectable Internal Error Mask Register 8.1.8. Correctable Internal Error Status Register 8.1.9. Correctable Internal Error Mask Register 8.1.10. SR-IOV Virtualization Extended Capabilities Registers Address Map
8.1.4. Intel Defined VSEC Capability Header x
8.1.4.1. Intel Defined Vendor Specific Header 8.1.4.2. Intel Marker 8.1.4.3. JTAG Silicon ID 8.1.4.4. User Configurable Device and Board ID
8.1.10. SR-IOV Virtualization Extended Capabilities Registers Address Map x
8.1.10.1. ARI Enhanced Capability Header 8.1.10.2. SR-IOV Enhanced Capability Registers 8.1.10.3. Initial VFs and Total VFs Registers 8.1.10.4. VF Device ID Register 8.1.10.5. Page Size Registers 8.1.10.6. VF Base Address Registers (BARs) 0-5 8.1.10.7. Secondary PCI Express Extended Capability Header 8.1.10.8. Lane Status Registers 8.1.10.9. Transaction Processing Hints (TPH) Requester Enhanced Capability Header 8.1.10.10. TPH Requester Capability Register 8.1.10.11. TPH Requester Control Register 8.1.10.12. Address Translation Services ATS Enhanced Capability Header 8.1.10.13. ATS Capability Register and ATS Control Register
9. Testbench and Design Example x
9.1. Endpoint Testbench 9.2. Test Driver Module 9.3. Root Port BFM Overview 9.4. BFM Procedures and Functions
9.1. Endpoint Testbench x
9.1.1. Endpoint Testbench for SR-IOV
9.3. Root Port BFM Overview x
9.3.1. BFM Memory Map 9.3.2. Configuration Space Bus and Device Numbering 9.3.3. Configuration of Root Port and Endpoint 9.3.4. Issuing Read and Write Transactions to the Application Layer
9.4. BFM Procedures and Functions x
9.4.1. ebfm_barwr Procedure 9.4.2. ebfm_barwr_imm Procedure 9.4.3. ebfm_barrd_wait Procedure 9.4.4. ebfm_barrd_nowt Procedure 9.4.5. ebfm_cfgwr_imm_wait Procedure 9.4.6. ebfm_cfgwr_imm_nowt Procedure 9.4.7. ebfm_cfgrd_wait Procedure 9.4.8. ebfm_cfgrd_nowt Procedure 9.4.9. BFM Configuration Procedures 9.4.10. BFM Shared Memory Access Procedures 9.4.11. BFM Log and Message Procedures 9.4.12. Verilog HDL Formatting Functions
9.4.9. BFM Configuration Procedures x
9.4.9.1. ebfm_cfg_rp_ep Procedure 9.4.9.2. ebfm_cfg_decode_bar Procedure
9.4.10. BFM Shared Memory Access Procedures x
9.4.10.1. Shared Memory Constants 9.4.10.2. shmem_write Task 9.4.10.3. shmem_read Function 9.4.10.4. shmem_display Verilog HDL Function 9.4.10.5. shmem_fill Procedure 9.4.10.6. shmem_chk_ok Function
9.4.11. BFM Log and Message Procedures x
9.4.11.1. ebfm_display Verilog HDL Function 9.4.11.2. ebfm_log_stop_sim Verilog HDL Function 9.4.11.3. ebfm_log_set_suppressed_msg_mask Task 9.4.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 9.4.11.5. ebfm_log_open Verilog HDL Function 9.4.11.6. ebfm_log_close Verilog HDL Function
9.4.12. Verilog HDL Formatting Functions x
9.4.12.1. himage1 9.4.12.2. himage2 9.4.12.3. himage4 9.4.12.4. himage8 9.4.12.5. himage16 9.4.12.6. dimage1 9.4.12.7. dimage2 9.4.12.8. dimage3 9.4.12.9. dimage4 9.4.12.10. dimage5 9.4.12.11. dimage6 9.4.12.12. dimage7
10. Troubleshooting and Observing the Link x
10.1. Troubleshooting 10.2. PCIe Link Inspector Overview
10.1. Troubleshooting x
10.1.1. Simulation Fails To Progress Beyond Polling.Active State 10.1.2. Hardware Bring-Up Issues 10.1.3. Link Training 10.1.4. Link Hangs in L0 State 10.1.5. Use Third-Party PCIe Analyzer
10.2. PCIe Link Inspector Overview x
10.2.1. PCIe* Link Inspector Hardware
10.2.1. PCIe* Link Inspector Hardware x
10.2.1.1. Enabling the PCIe* Link Inspector 10.2.1.2. Launching the PCIe* Link Inspector 10.2.1.3. The PCIe* Link Inspector LTSSM Monitor 10.2.1.4. Accessing the Configuration Space and Transceiver Registers 10.2.1.5. Additional Status Commands
10.2.1.3. The PCIe* Link Inspector LTSSM Monitor x
10.2.1.3.1. LTSSM Monitor Registers 10.2.1.3.2. ltssm_save2file <file_name> 10.2.1.3.3. ltssm_file2console 10.2.1.3.4. ltssm_debug_check 10.2.1.3.5. ltssm_display <num_states> 10.2.1.3.6. ltssm_save_oldstates
10.2.1.4. Accessing the Configuration Space and Transceiver Registers x
10.2.1.4.1. PCIe* Link Inspector Commands 10.2.1.4.2. NPDME PLL and Channel Commands 10.2.1.4.3. Register Address Map
10.2.1.5. Additional Status Commands x
10.2.1.5.1. Displaying PLL Lock and Calibration Status Registers
A. PCI Express Core Architecture x
A.1. Transaction Layer A.2. Data Link Layer A.3. Physical Layer
D. Document Revision History x
D.1. Document Revision History for the Intel® L- and H-Tile Avalon® Streaming and Single-Root I/O Virtualization (SR-IOV) IP for PCI Express* User Guide
1. Introduction
2. Quick Start Guide
3. Interface Overview
4. Parameters
5. Designing with the IP Core
6. Block Descriptions
7. Interrupts
8. Registers
9. Testbench and Design Example
10. Troubleshooting and Observing the Link
A. PCI Express Core Architecture
B. TX Credit Adjustment Sample Code
C. Root Port Enumeration
D. Document Revision History

6.1.6. TX Credit Interface

Before a TLP can be transmitted, flow control logic verifies that the link partner's RX port has sufficient buffer space to accept it. The TX Credit interface reports the link partner's available RX buffer space to the Application. It reports the space available in units called Flow Control credits.

Flow Control credits are defined for the following TLP categories:

  • Posted transactions - TLPs that do not require a response
  • Non-Posted transactions - TLPs that require a completion
  • Completions - TLPs that respond to non-posted transactions
Table 35.  Categorization of Transactions Types
TLP Type Category
Memory Write Posted

Memory Read

Memory Read Lock

 Non-posted

I/O Read

I/O Write

 Non-posted

Configuration Read

Configuration Write

 Non-posted
Message Posted

Completions

Completions with Data

Completion Locked

Completion Lock with Data

 Completions
Fetch and Add AtomicOp Non-posted
Table 36.  Flow Control CreditsThe following table translates flow control credits to dwords. The PCI Express Base Specification defines a dword as four bytes.
Credit Type Number of Dwords
Header credit - completions 4 dwords
Header credit - requests 5 dwords
Data credits 4 dwords
Table 37.  TX Flow Control Credit InterfaceThe IP core provides TX credit information to the Application Layer. To optimize performance, the Application can perform credit-based checking before submitting requests for transmission, and reorder packets to improve throughput. The IP core always checks for sufficient TX credits before transmitting any TLP.

Signal

Direction

Description

tx_ph_cdts[7:0]

Output

 Header credit net value for the flow control (FC) posted requests.
tx_pd_cdts[11:0]

Output

 Data credit net value for the FC posted requests.
tx_nph_cdts[7:0]

Output

Header credit net value for the FC non-posted requests.

tx_npd_cdts[11:0] L-Tile

Output

Data credit net value for the FC non-posted requests.

The tx_npd_cdts[11:0] is not available for H-Tile devices. You can monitor the non-posted header credits to determine if there is sufficient space to transmit the next non-posted data TLP.

tx_cplh_cdts[7:0]

Output

 Header credit net value for the FC Completion. A value of 0xFF indicates infinite Completion header credits.
tx_cpld_cdts[11:0]L-Tile

Output

Data credit net value for the FC Completion. A value of 0xFF indicates infinite Completion data credit.

The tx_cpld_cdts[11:0] is not available for H-Tile devices. You can monitor the completion header credits to determine if there is sufficient space to transmit the next non-posted data TLP. The completion TLP size is either the request data size or 64 bytes when the completion is split.

For Root Ports or non peer-to-peer Endpoints as the link partner, assume that this credit is infinite.

tx_hdr_cdts_consumed[1:0]

Output

Asserted for 1 coreclkout_hip cycle, for each header credit consumed by the application layer traffic. Note that credits the Hard IP consumes for internally generated Completions or Messages are not tracked in this signal.

For the Gen3 x16 512-bit interface, tx_hdr_cdts_consumed[1] is for the higher bus and tx_hdr_cdts_consumed[0] is for the lower bus.

There is only one tx_hdr_cdts_consumed signal for the 256-bit interface.

tx_data_cdts_consumed[1:0]

Output

Asserted for 1 coreclkout_hip cycle, for each data credit consumed. Note that credits the Hard IP consumes for internally generated Completions or Messages are not tracked in this signal.

For the Gen3 x16 512-bit interface, tx_data_cdts_consumed[1] is for the higher bus and tx_data_cdts_consumed[0] is for the lower bus.

There is only one tx_data_cdts_consumed signal for the 256-bit interface.

tx_cdts_type[<n>-1:0] Output

Specifies the credit type shown on the tx_cdts_data_value[1:0] bus. The following encodings are defined:

  • 2'b00: Posted credits

  • 2'b01: Non-posted credits3

  • 2'b10: Completion credits

  • 2'b11: Reserved

For the Gen3 x16 512-bit interface, tx_cdts_type[3:2] is for the higher bus and tx_cdts_type[1:0] is for the lower bus.

tx_cdts_data_value[3:0] L-Tile, 16 lanes

tx_cdts_data_value[1:0] L-Tile, 8 lanes or fewer

tx_cdts_data_value[1:0] H-Tile, 16 lanes

tx_cdts_data_value H-Tile, 8 lanes or fewer

Output

For H-Tile: 1 = 2 data credits consumed; 0 = 1 data credit consumed.

For L-Tile: The value of tx_cdts_data_value+1 specifies the data credit consumed.

For both H- and L-Tiles: Only valid when tx_data_cdts_consumed asserts.

For the Gen3 x16 512-bit interface, tx_cdts_data_value[1] is for the higher bus and tx_cdts_data_value[0] is for the lower bus.

3 The PCIe IP core does not consume non-posted credits.
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