L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 10/27/2023
Public

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Document Table of Contents

6.1.19. Serial Data Interface

The IP core supports 1, 2, 4, 8, or 16 lanes.
Table 48.  Serial Data Interface

Signal

Direction

Description

tx_out[<n-1>:0]

Output

Transmit serial data output.
rx_in[<n-1>:0]

Input

Receive serial data input.