L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 10/27/2023
Public

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Document Table of Contents

6.2.1. Error Handling

When the IP core detects an error in a received TLP, it generates a Completion. It sets the Completion status set to Completer Abort (CA) or Unsupported Request (UR).

The IP Core completes the following actions when it detects an error in a received TLP:

  • Discards the TLP.
  • Generates a Completion (for non-posted requests) with the Completion status set to CA or UR.
  • Sets the corresponding status bits in the PCI Status register and the PCIe Device Status register.
  • Sets the corresponding status bits and header log in the AER registers if AER is enabled.
  • Indicates the Error event to the upstream component.
    • For Endpoints, the IP core sends an error Message upstream.
    • For Root Ports, the IP core asserts app_serr_out asserts to the Application Layer) when it detects an error or receives an error Message from a downstream component.
      Note: The error Message from the downstream component is also forwarded on the Avalon® -ST RX interface. The Application Layer may choose to ignore this information.