L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 10/27/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.1.3. Avalon-ST 512-Bit RX Interface

The Application Layer receives data from the Transaction Layer of the PCI Express* IP core over the Avalon-ST RX interface. The 512-bit interface supports Gen3 x16 variants and uses a 250 MHz clock, simplifying timing closure.

The 512-bit interface supports two locations for the beginning of a TLP, bit[0] and bit[256]. The interface supports two TLPs per cycle only when an end-of-packet cycle occurs in the lower 256 bits. In other words, a TLP can start on bit [256] only if a rx_st_eop pulse occurs in the lower 256 bits.

Note: This interface is not strictly Avalon® -compliant because it supports two rx_st_sop signals and two rx_st_eop signals per cycle.
Table 32.  512‑Bit Avalon-ST RX Datapath

Signal

Direction

Description

rx_st_data_o[511:0]

Output

Receive data bus. The Application Layer receives data from the Transaction Layer on this bus. For large TLPs, the Application Layer drives 512-bit data on rx_st_data[511:0] until the end-of-packet cycle.

For TLPs with an end-of-packet cycle in the lower 256 bits, the 512-bit interface supports a start-of-packet cycle in the upper 256 bits.

rx_st_sop[1:0]

Output

Signals the first cycle of the TLP when asserted in conjunction the corresponding bit of rx_st_valid. The following encodings are defined:
  • rx_st_sop[1]: When asserted, indicates the start of a TLP on rx_st_data[511:256].
  • rx_st_sop[0]: When asserted, indicates the start of a TLP on rx_st_data[255:0].

rx_st_eop[1:0]

Output

Signals the last cycle of the TLP when asserted in conjunction with the corresponding bit of rx_st_valid[1:0]. The following encodings are defined:

  • rx_st_eop[1]: When asserted, signals the end of a TLP on rx_st_data[511:256].
  • rx_st_sop[0]: When asserted, signals the end of a TLP on rx_st_data[255:0].

rx_st_ready_i

Input

Indicates that the Application Layer is ready to accept data. The Application Layer deasserts this signal to apply backpressure to the data stream.

rx_st_valid_o[1:0]

Output

Qualifies rx_st_data_o into the Application Layer.

The rx_st_ready_i to rx_st_valid_o[1:0] latency for Stratix® 10 devices is 18 cycles. When rx_st_ready_i deasserts, rx_st_valid_o[1:0] will deassert within 18 cycles. When rx_st_ready_i reasserts, rx_st_valid_o will reassert within 18 cycles if there is more data to send. To achieve the best throughput, Intel recommends that you size the RX buffer in your application logic to avoid the deassertion of rx_st_ready_o.

The Relationship Between rx_st_ready and rx_st_valid for the 512-bit Avalon-ST Interface timing diagram below illustrates the relationship between rx_st_ready_i and rx_st_valid_o.

rx_st_bar_range_o[5:0]

Output

Specifies the BAR for the TLP being output. The following encodings are defined:
  • rx_st_bar_range_o[5:3]: Specifies BAR for rx_st_data[511:256].
  • rx_st_bar_range_o[2:0]: Specifies BAR for rx_st_data[255:0].
For each BAR range, the following encodings are defined:
  • 000: Memory BAR 0
  • 001: Memory BAR 1
  • 010: Memory BAR 2
  • 011: Memory BAR 3
  • 100: Memory BAR 4
  • 101: Memory BAR 5
  • 110: I/O BAR
  • 111: Expansion ROM BAR

These outputs are valid when both rx_st_sop and rx_st_valid are asserted.

rx_st_empty_o[5:0] Output

Specifies the number of dwords that are empty during cycles when the rx_st_eop_o[1:0] signal is asserted. Not valid when rx_st_eop[1:0] is deasserted. The following encodings are defined:

  • rx_st_empty_o[5:3]: Specifies empty dwords for the high-order packet.
  • rx_st_empty_o[2:0]: Specifies empty dwords for the low-order packet.
rx_st_parity_o[63:0] Output Byte parity for rx_st_data_o. Bit 0 corresponds to rx_st_data_o[7:0], bit 1 corresponds to rx_st_data_o[15:8] and so on.
rx_st_vf_active[1:0] H-Tile Output

When asserted, the received TLP targets a VF bar. Valid when rx_st_sop is asserted. When deasserted, the TLP targets a PF and the rx_st_func_num port drives the physical function number.

For the 512-bit interface, Bit [0] corresponds to the rx_st_data[255:0] and bit 1 corresponds to rx_st_data[511:256]

Valid when multiple physical functions are enabled.

rx_st_func_num[3:0] H-Tile

Output
  • rx_st_func_num[3:2]: Specifies the physical function number for rx_st_data[511:256].
  • rx_st_func_num[1:0]: Specifies the physical function number for rx_st_data[255:0]

rx_st_vf_num[log2 <x>)-1:0] H-Tile

Output

Specifies the target VF number for the received TLP. The application uses this information for both request and completion TLPs. For completion TLPs, specifies the VF number of the requester for this completion TLP. <x> is the number of VFs.

The following encodings are defined:

  • rx_st_vf_num[21:11]: Specifies the VF number for rx_st_data[511:256]
  • rx_st_vf_num[10:0]: Specifies the VF number for rx_st_data[255:0]

Valid when rx_st_vf_active is asserted. If the TLP targeting at VF[<m>, <n>] this bus carries the VF<n> information.

Valid when multiple virtual functions are enabled.

Figure 42. Relationship Between rx_st_ready and rx_st_valid for the 512-bit Avalon-ST Interface