L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 10/27/2023
Public

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3.12. Reset

This interface indicates when the clocks are stable and FPGA configuration is complete.

The PCIe IP core receives the following inputs that can be used for the reset purpose:
  • pin_perst is the active low reset driven from the PCIe motherboard. Logic on the motherboard autonomously generates this fundamental reset signal.
  • npor is an active low reset signal. The Application drives this reset signal.
  • ninit_done is an active low input signal. A "1" indicates that the FPGA device is not yet fully configured. A "0" indicates the device has been configured and is in normal operating mode. To use the ninit_done input, instantiate the Reset Release Intel FPGA IP in your design and use its ninit_done output to drive the input of the Avalon® streaming IP for PCIe. For more details on how to use this input, refer to Including the Reset Release Intel® FPGA IP in Your Design.

The PCIe IP core reset logic requires a free-running clock input. This free-running clock becomes stable after the secure device manager (SDM) block asserts iocsrrdy_dly indicating that the I/O Control and Status registers programming is complete.